Display link clocking method and apparatus

1. An apparatus comprising:

a clock circuit that is operative to provide a common clock signal synthesized from a reference clock signal; and

a plurality of display interface circuits that are operative to provide a plurality of respective display link clock signals in response to the common clock signal, wherein a first of the plurality of display link clock signals is at a different clock speed than the common clock signal while a second of the plurality of display link clock signals is simultaneously at a different clock speed than both the first of the plurality of display link clock signals and the common clock signal,

wherein the clock speeds of the first and second of the plurality of display link clock signals are adjusted in response to display configuration information from each of a first and a second of a plurality of displays respectively for simultaneously driving the first and the second of the plurality of displays respectively.

2. The apparatus of claim 1 wherein each of the plurality of display interface circuits comprises a clock signal adjuster circuit that is operative to provide the display link clock signal by selectively scaling the common clock signal.

3. The apparatus of claim 1 further comprising a display interface link rate control circuit that is operative to control the clock signal adjuster circuit to scale the common clock signal based on the display configuration information from each of the first and the second of the plurality of displays respectively.

4. The apparatus of claim 1 wherein each respective link clock signal is operative to drive a respective display link.

5. The apparatus of claim 1 wherein each of the first and the second of the plurality of displays operate using different timing schemes.

6. The apparatus of claim 1 wherein the common clock signal is scaled to have the respective clock speed that matches a link clock speed of the respective device in response to the display configuration information.

7. The apparatus of claim 1 wherein the display configuration information includes at least one of a type and make information of the respective display.

8. A method comprising:

providing a common clock signal synthesized from a reference clock signal;

providing a plurality of display link clock signals in response to the common clock signal, wherein a first of the plurality of display link clock signals is at a different clock speed than the common clock signal while a second of the plurality of display link clock signals is simultaneously at a different clock speed than both the first of the plurality of display link clock signals and the common clock signal,

wherein the clock speeds of the first and second of the plurality of display link clock signals are adjusted in response to display configuration information from each of a first and a second of a plurality of displays respectively for simultaneously driving the first and the second of the plurality of displays respectively.

9. The method of claim 8 wherein providing the plurality of display link clock signals comprises selectively scaling the common clock signal.

10. The method of claim 9 selectively scaling the common clock signal is based on the display configuration information from each of the first and the second of the plurality of displays respectively.

11. A non-transitory computer readable medium comprising information that when executed by at least one processor causes the at least one processor to layout an integrated circuit that comprises:

a clock circuit that is operative to provide a common clock signal synthesized from a reference clock signal; and

a plurality of display interface circuits that are operative to provide a plurality of respective link clock signals in response to the common clock signal, wherein a first of the plurality of link clock signals is at a different clock speed than the common clock signal while a second of the plurality of link clock signals is simultaneously at a different clock speed than both the first of the plurality of link clock signals and the common clock signal,

wherein the clock speeds of the first and second of the plurality of link clock signals are adjusted in response to display configuration information from each of a first and a second of a plurality of displays respectively for simultaneously driving the first and the second of the plurality of displays respectively.

12. The computer readable medium of claim 11 wherein each of the plurality of display interface circuits comprises a clock signal adjuster circuit that is operative to provide the link clock signal by selectively scaling the common clock signal.

13. The computer readable medium of claim 11 further comprising a display interface link rate control circuit that is operative to control the clock signal adjuster circuit to scale the common clock signal based on the display configuration information from each of the first and the second of the plurality of displays respectively.

14. The computer readable medium of claim 11 wherein the display configuration information includes at least one of a type and make information of the respective display.

15. The computer readable medium of claim 11 wherein the information comprises hardware description language.

16. The computer readable medium of claim 11 wherein each of the first and the second of the plurality of displays operate using different timing schemes.

17. The method of claim 8 wherein each of the first and the second of the plurality of displays operate using different timing schemes.

18. The method of claim 8 wherein the display configuration information includes at least one of a type and make information of the respective display.

19. The method of claim 11 wherein the display configuration information includes at least one of a type and make information of the respective display.