IP Library Granted Patent US 8,505,001
Granted Patent B2
US 8,505,001 · App. 12/868,192 · Granted Aug 6, 2013

Method and system for utilizing data flow graphs to compile shaders

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Quick Facts
Patent No.
US 8,505,001
App. No.
12/868,192
Granted
Aug 6, 2013
Kind
B2
Abstract

A method and system are provided in which one or more processors may be operable to generate an intermediate representation of a shader source code, wherein the intermediate representation comprises one or more whole-program data flow graph representations of the shader source code. The one or more processors may be operable to generate machine code based on the generated intermediate representation of the shader source code. The one or more whole-program data flow graph representations of the shader source code may be generated utilizing a compiler front end. The machine code may be generated utilizing a compiler back end. The generated machine code may be executable by a graphics processor. The generated machine code may be executable by a processor comprising a single-instruction multiple-data (SIMD) architecture. The generated machine code may be executable to perform coordinate and/or vertex shading of image primitives.

Claims (28)

1. A method for code processing, the method comprising:

performing by one or more processors:

generating an intermediate representation of a shader source code, wherein said intermediate representation comprises one or more whole-program data flow graph representations of said shader source code; and

generating in said one or more processors, machine code based on said generated intermediate representation of said shader source code.

2. The method according to claim 1 , comprising generating said one or more whole-program data flow graph representations of said shader source code utilizing a compiler front end.

3. The method according to claim 1 , wherein said generated machine code is executable by a processor comprising a single-instruction multiple-data (SIMD) architecture.

4. The method according to claim 1 , wherein said generated machine code is executable by a graphics processor.

5. The method according to claim 1 , wherein said generated machine code is executable by a graphics processor comprising a fixed-cycle-pipeline architecture.

6. The method according to claim 1 , wherein said generated machine code is executable to perform vertex shading of image primitives.

7. The method according to claim 1 , wherein said generated machine code is executable to perform coordinate shading of image primitives.

8. The method according to claim 1 , wherein said intermediate representation is an executable representation of said shader source code.

9. The method according to claim 1 , wherein said shader source code comprises a vertex shader source code.

10. The method according to claim 1 , comprising generating said machine code utilizing a compiler back end.

11. A non-transitory computer-readable medium having stored thereon, a computer program having at least one code section for code processing, the at least one code section being executable by a computer for causing the computer to perform steps comprising:

generating an intermediate representation of a shader source code, wherein said intermediate representation comprises one or more whole-program data flow graph representations of said shader source code; and

generating machine code based on said generated intermediate representation of said shader source code.

12. The non-transitory computer-readable medium according to claim 11 , wherein said at least one code section comprises code for generating said one or more whole-program data flow graph representations of said shader source code utilizing a compiler front end.

13. The non-transitory computer-readable medium according to claim 11 , wherein said generated machine code is executable by a processor comprising a single-instruction multiple-data (SIMD) architecture.

14. The non-transitory computer-readable medium according to claim 11 , wherein said generated machine code is executable by a graphics processor comprising a fixed-cycle-pipeline architecture.

15. The non-transitory computer-readable medium according to claim 11 , wherein said generated machine code is executable to perform vertex shading of image primitives.

16. The non-transitory computer-readable medium according to claim 11 , wherein said generated machine code is executable to perform coordinate shading of image primitives.

17. The non-transitory computer-readable medium according to claim 11 , wherein said intermediate representation is an executable representation of said shader source code.

18. The non-transitory computer-readable medium according to claim 11 , wherein said shader source code comprises a vertex shader source code.

19. The non-transitory computer-readable medium according to claim 11 , wherein said at least one code section comprises code for generating said machine code utilizing a compiler back end.

20. A method for code processing, the method comprising:

performing by one or more processors:

generating a whole-program data flow graph representation of a vertex shader source code utilizing a compiler front end; and

generating in said one or more processors, machine code based on said generated whole-program data flow graph representation utilizing a compiler back end.

Assignments (3)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →