Method and system for secure communication between processor partitions
View Patent ↗A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message.
1. A method, comprising:
managing the process of switching between a plurality of independent tasks;
receiving an interrupt from a sender and a first notification of a pending message;
converting blocks of memory from free blocks to data blocks;
receiving at least one further interrupt from a plurality of receivers and at least one further notification of that the pending message has been read;
converting the data blocks back to free blocks; and
designating the blocks of memory as free blocks after the at least one further interrupt has been received, wherein the designating occurs after each of the further interrupts are received from all of the plurality of receivers.
2. The method of claim 1 , further comprising:
changing a sender access from read-write access to read-only access while the message is pending; and
changing a sender access from read-only access back to read-write access once the pending message has been sent.
3. The method of claim 1 , further comprising:
providing, by an interprocess communication (“IPC”) control facility, control access to a plurality of IPC channels by at least one of the sender and the receiver.
4. The method of claim 1 , wherein the plurality of independent tasks are run on a plurality of virtual processors, wherein each virtual processor includes at least one virtual board connected via a corresponding channel.
5. The method of claim 4 , wherein the method is performed by a hypervisor providing integrity against faulty data in any one of the plurality of virtual boards.
6. The method of claim 1 , further comprising:
monitoring, by a hypervisor, the use of processing time by at least one of the sender and the plurality of receivers.
7. The method of claim 1 , wherein the message is directed to a plurality of recipients as a multicast transmission.
8. The method of claim 3 , wherein the IPC control facility ensures proper directionality along the IPC channels.
9. The method of claim 3 , wherein the IPC control facility controls path integrity for data transmission and synchronization between the sender and the plurality of receivers.
10. The method of claim 3 , wherein the IPC control facility is an integrated component of the hypervisor.
11. The method of claim 4 , wherein the IPC control facility provides isolation between the virtual boards.
12. A system, comprising:
a hypervisor managing the process of switching between a plurality of independent tasks, receiving an interrupt from a sender and a first notification of a pending message, converting blocks of memory from free blocks to data blocks, receiving at least one further interrupt from a plurality of receivers and at least one further notification of that the pending message has been read, converting the data blocks back to free blocks, and designating the blocks of memory as free blocks after the at least one further interrupt has been received, wherein the designating occurs after each of the further interrupts are received from all of the plurality of receivers; and
a IPC control facility providing for control access to IPC channels by boards.
13. The system of claim 12 , wherein the hypervisor changes a sender access from read-write access to read-only access while the message is pending, and changes a sender access from read-only access back to read-write access once the pending message has been sent.
14. The system of claim 12 , wherein the plurality of independent tasks are run on a plurality of virtual processors, wherein each virtual processor includes at least one virtual board connected via a corresponding channel.
15. The system of claim 12 , wherein the hypervisor monitors use of processing time by at least one of the sender and the plurality of receivers.
16. The system of claim 12 , wherein the message is directed to a plurality of recipients as a multicast transmission.
17. The system of claim 12 , wherein the IPC control facility ensures proper directionality along the IPC channels.
18. The system of claim 12 , wherein the IPC control facility controls path integrity for data transmission and synchronization between the sender and the plurality of receivers.
19. The system of claim 14 , wherein the IPC control facility provides isolation between the virtual boards.
20. A memory storing a set of instructions and a processor executing the instructions, the instructions being operable to:
manage the process of switching between a plurality of independent tasks;
receive an interrupt from a sender and a first notification of a pending message;
convert blocks of memory from free blocks to data blocks;
receive at least one further interrupt from a plurality of receivers and at least one further notification of that the pending message has been read;
convert the data blocks back to free blocks;
provide for control access to IPC channels by boards; and
designate the blocks of memory as free blocks after the at least one further interrupt has been received, wherein the designating occurs after each of the further interrupts are received from all of the plurality of receivers.