Granted Patent B2

US 8,621,194 · App. 12/872,733 · Granted Dec 31, 2013

Abstract

Claims (31)

1. A system for booting a processor from NAND flash, comprising:

a NAND agnostic boot controller; and

a NAND flash device, wherein the NAND flash device further comprises a boot wrapper storing boot code in a predetermined format and a block walking structure configured to identify a process for moving from a current image of the NAND flash device to a next sequential image of the NAND flash device.

2. The system of claim 1 wherein the boot wrapper further comprises a page header structure configured to identify a start of each of a plurality of pages of the NAND flash device.

3. The system of claim 2 wherein the NAND agnostic boot controller comprises a page header processor configured to read the page header structure to identify the start of each of the plurality of pages of the NAND flash device.

4. The system of claim 2 wherein the NAND agnostic boot controller comprises a page header processor configured to read the start of each of the plurality of pages of the NAND flash device from the boot header structure of the boot wrapper.

5. The system of claim 1 wherein the boot wrapper further comprises a page payload structure configured to provide an array of data words.

6. The system of claim 5 wherein the NAND agnostic boot controller comprises a page payload processor configured to read the array of data words.

7. The system of claim 1 wherein the boot wrapper further comprises a page walking structure configured to identify a process for moving from a current page of the NAND flash device to a next sequential page of the NAND flash device.

8. The system of claim 7 wherein the NAND agnostic boot controller comprises a page walking processor configured to move from the current page of the NAND flash device to the next sequential page of the NAND flash device.

9. The system of claim 7 wherein the NAND agnostic boot controller comprises a page walking processor configured to read the process for moving from the current page of the NAND flash device to the next sequential page of the NAND flash device from the boot wrapper and to automatically implement the process.

10. The system of claim 1 wherein the NAND agnostic boot controller comprises a block walking processor configured to move from the current image of the NAND flash device to the next sequential image of the NAND flash device.

11. The system of claim 1 wherein the NAND agnostic boot controller comprises a block walking processor configured to read the process for moving from the current image of the NAND flash device to the next sequential image of the NAND flash device from the boot wrapper and to automatically implement the process.

12. The system of claim 1 wherein the boot wrapper further comprises a page payload structure storing a number of boot image dwords.

13. The system of claim 12 wherein the NAND agnostic boot controller comprises a page payload processor configured to read the number of boot image dwords from the boot wrapper and to process the boot wrapper using the number of boot image dwards.

14. The system of claim 1 wherein the boot wrapper further comprises a page walking structure storing a number of initialization operations.

15. The system of claim 14 wherein the NAND agnostic boot controller comprises a page walking processor configured to read the number of initialization operations from the boot wrapper and to process the boot wrapper using the number of initialization operations.

16. The system of claim 1 wherein the NAND agnostic boot controller is configured to initialize a running block page index value to zero, open a physical NAND page identified by block page index of the boot wrapper, read a page header structure to identify a start of a NAND page, process a signature field to identify a static value having a predetermined value, and process an image page index field of a boot wrapper to identify a current page index of an image.

17. The system of claim 16 wherein the NAND agnostic boot controller is further configured to process a block page index field to determine a current physical NAND page number, process an image identifier field to extract an image identifier code and to determine whether an image is corrupt.

18. The system of claim 17 wherein the NAND agnostic boot controller is further configured to determine if a current section of a boot wrapper is valid and to increment a block page index if the current section of the boot wrapper is invalid.

19. A system for booting a processor from NAND flash, comprising:

a NAND flash device, wherein the NAND flash device further comprises a boot wrapper storing boot code in a predetermined format, the boot wrapper further comprising:

a page header structure for identifying a start of each of a plurality of pages of the NAND flash device;

a block walking structure for identifying a process for moving from a current image of the NAND flash device to a next sequential image of the NAND flash device;

a page payload structure for providing an array of data words; and

a page walking structure for identifying a process for moving from a current page of the NAND flash device to a next sequential page of the NAND flash device; and

a NAND agnostic boot controller further comprising:

a page header processor for reading the page header structure to identify the start of each of the plurality of pages of the NAND flash device;

a block walking processor moving from the current image of the NAND flash device to the next sequential image of the NAND flash device;

a page payload processor for reading the array of data words; and

a page walking processor for moving from the current page of the NAND flash device to the next sequential page of the NAND flash device.

Assignments (9)