Distributing clock associated with a wired communication channel over wireless interfaces by sending a clock correction message to the receiving side
View Patent ↗A clock extractor extracts clock frequency f 2 , from a wired data connection. A clock error estimator estimates a first clock frequency error between clock frequency f 2 and a clock frequency f 1 associated with a local clock of the transmitter. A transmitter sends the first clock frequency error, as a message to a receiver. The transmitter uses a wireless transmitter interface, including a modulator and transmitter radio. The wireless transmitter interface is clocked at clock frequency f 1 . The transmitter sends data to the receiver. A wireless receiver interface includes a de-modulator and receiver radio. The wireless receiver interface reconstructs clock frequency f 1 . A clock adder adds the reconstructing clock frequency f 1 to the first clock frequency error, resulting in a synthesized clock frequency f 2 . The receiver clocks a second wired data connection, using the synthesized clock frequency f 2.
1. A method for distributing clock over wireless link, comprising:
extracting, by a transmitter, clock frequency f 2 from a wired data connection feeding the transmitter with data clocked at the clock frequency f 2 ;
estimating a first clock frequency error between the clock frequency f 2 and a clock frequency f 1 associated with a local clock of the transmitter;
sending the first clock frequency error, as a message to a receiver, by the transmitter, over a wireless link;
using a wireless transmitter interface comprising a modulator and transmitter radio, the wireless transmitter interface clocked at the clock frequency f 1 to send data from the transmitter to the receiver over the wireless link;
reconstructing clock frequency f 1 by a wireless receiver interface comprising a de-modulator and receiver radio as a reconstructed clock frequency f 1 estimating a second clock frequency error between the reconstructed clock frequency f 1 and a clock frequency f 3 associated with a local clock of the receiver;
calculating, by the receiver, the first clock frequency error plus the second clock frequency error, resulting in a third clock frequency error equal to the clock frequency f 2 minus the clock frequency f 3 ;
adding the clock frequency f 3 to the third clock frequency error, by the receiver, resulting in a synthesized clock frequency f 2 ; and
clocking a second wired data connection at the receiver, using the synthesized clock frequency f 2 .
2. The method of claim 1 , wherein the wired data connection feeding the transmitter and the second wired data connection at the receiver are both Ethernet wired connections.
3. The method of claim 1 , wherein the second wired data connection is used to output data received by the de-modulator from the transmitter.
4. The method of claim 1 , wherein adding the clock frequency f 3 to the third clock frequency error is done using Direct Digital Synthesis (DDS).
5. The method of claim 4 , wherein the DDS is a discrete component in the receiver.
6. The method of claim 1 , wherein adding the clock frequency f 3 to the third clock frequency error is done numerically by a processor.
7. The method of claim 6 , wherein the processor is also used to for de-modulation.
8. The method of claim 6 , wherein adding the clock frequency f 3 to the third clock frequency error is done using Direct Digital Synthesis (DDS).
9. The method of claim 1 , wherein using a wireless transmitter interface clocked at the clock frequency f 1 comprises using the modulator with data symbols or spreading chips of duration associated with the clock frequency f 1 to send the data from the transmitter to the receiver.
10. The method of claim 9 , wherein the modulator uses a modulation selected from a group of OFDM, Single Carrier QAM, and CDMA.
11. The method of claim 1 , wherein estimating the clock frequency error between the reconstructed clock frequency f 1 and the clock frequency f 3 is done by counting clock cycles of the reconstructed clock frequency f 1 and the clock frequency f 3 over a period, and comparing the counts.
12. The method of claim 1 , wherein estimating the clock frequency error between the clock frequency f 2 and the clock frequency f 1 is done by counting clock cycles of the clock frequency f 2 and the clock frequency f 1 over a period, and comparing the counts.
13. A method for distributing clock over wireless link, comprising:
extracting, by a transmitter, clock frequency f 2 from a wired data connection feeding the transmitter with data clocked at the clock frequency f 2 ;
estimating a first clock frequency error between the clock frequency f 2 and a clock frequency f 1 associated with a local clock of the transmitter;
sending the first clock frequency error, as a message to a receiver, by the transmitter, over a wireless link;
using a wireless transmitter interface comprising a modulator and transmitter radio, the wireless transmitter interface clocked at the clock frequency f 1 to send data from the transmitter to the receiver over the wireless link;
reconstructing clock frequency f 1 by a wireless receiver interface comprising a de-modulator and receiver radio as a reconstructed clock frequency f 1 adding the reconstructing clock frequency f 1 to the first clock frequency error, by the receiver, resulting in a synthesized clock frequency f 2 ; and
clocking a second wired data connection at the receiver, using the synthesized clock frequency f 2 .
14. The method of claim 13 , wherein the wired data connection feeding the transmitter and the second wired data connection at the receiver are both Ethernet wired connections.
15. The method of claim 13 , wherein the second wired data connection is used to output data received by the de-modulator from the transmitter.
16. The method of claim 13 , wherein adding the reconstructing clock frequency f 1 to the first frequency error is done using Direct Digital Synthesis (DDS).
17. The method of claim 16 , wherein the DDS is a discrete component in the receiver.
18. The method of claim 13 , wherein adding the reconstructed clock frequency f 1 to the first frequency error is done numerically by a processor.
19. The method of claim 18 , wherein the processor is also used to for de-modulation.
20. The method of claim 18 , wherein adding the reconstructed clock frequency f 1 to the first frequency error is done using Direct Digital Synthesis (DDS).
21. The method of claim 13 , wherein using a modulator clocked at the clock frequency f 1 comprises using data symbols or spreading chips of duration associated with the clock frequency f 1 to send the data from the transmitter to the receiver.
22. The method of claim 21 , wherein the modulator uses a modulation selected from a group of OFDM, Single Carrier QAM, and CDMA.
23. The method of claim 13 , wherein estimating the clock frequency error between the clock frequency f 2 and the clock frequency f 1 is done by counting clock cycles of the clock frequency f 2 and the clock frequency f 1 over a period, and comparing the counts.