IP Library Granted Patent US 8,405,141
Granted Patent B2
US 8,405,141 · App. 12/875,678 · Granted Mar 26, 2013

Nonvolatile semiconductor memory device and method for manufacturing same

Inventors: Toru Matsuda (Mie-ken, JP); Kazuyuki Higashi (Kanagawa-ken, JP)
Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,405,141
App. No.
12/875,678
Granted
Mar 26, 2013
Kind
B2
Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, an insulating film, a non-doped semiconductor film, a semiconductor pillar, a charge storage film, a contact, and a spacer insulating film. The stacked body is provided on the substrate. The stacked body includes a plurality of doped semiconductor films stacked. The insulating film is provided between the doped semiconductor films in a first region. The non-doped semiconductor film is provided between the doped semiconductor films in a second region. The semiconductor pillar pierces the stacked body in a stacking direction of the stacked body in the first region. The charge storage film is provided between the doped semiconductor film and the semiconductor pillar. The contact pierces the stacked body in the stacking direction in the second region. The spacer insulating film is provided around the contact.

Claims (27)

1. A nonvolatile semiconductor memory device comprising:

a substrate;

a stacked body provided on the substrate, the stacked body including a plurality of doped semiconductor films stacked;

an insulating film provided between the doped semiconductor films in a first region;

a non-doped semiconductor film provided between the doped semiconductor films in a second region;

a semiconductor pillar piercing the stacked body in a stacking direction of the stacked body in the first region;

a charge storage film provided between the doped semiconductor film and the semiconductor pillar;

a contact piercing the stacked body in the stacking direction in the second region; and

a spacer insulating film provided around the contact.

2. The device according to claim 1 , further comprising:

an insulating plate provided in part of a portion located inside the first region and in a portion along an outer edge of the first region in the stacked body, the insulating plate piercing the stacked body in the stacking direction.

3. The device according to claim 2 , wherein distance between the portion of the insulating plate formed along the outer edge of the first region and the contact is longer than distance between the portion of the insulating plate formed inside the first region and the semiconductor pillar.

4. The device according to claim 2 , further comprising:

a back gate electrode provided between the substrate and the stacked body in the first region; and

a connecting member provided in the back gate electrode and connecting lower ends of two adjacent ones of the semiconductor pillars to each other,

part of the insulating plate being located between the two adjacent semiconductor pillars.

5. The device according to claim 1 , wherein

the doped semiconductor film is made of silicon doped with boron,

the non-doped semiconductor film is made of non-doped silicon, and

the insulating film is made of silicon oxide.

6. The device according to claim 1 , further comprising:

a block insulating film provided between the doped semiconductor film and the charge storage film; and

a tunnel insulating film provided between the charge storage film and the semiconductor pillar.

7. The device according to claim 1 , further comprising:

a tunnel insulating film provided between the charge storage film and the semiconductor pillar,

the insulating film being located also between the doped semiconductor film and the charge storage film.

8. The device according to claim 1 , wherein the second region is a frame-shaped region surrounding the first region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2010
From: MATSUDA, TORU; HIGASHI, KAZUYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 024939/0934 →
Priority Claims (1)
JP 2010-013372 · Jan 25, 2010 · national
Continuity (1)
Related Publication 20110180866A1 · Jul 28, 2011