ANTICOUNTERFEITING SYSTEM AND METHOD FOR INTEGRATED CIRCUITS
An integrated circuit die comprises a device layer comprising a plurality of semiconductor devices; an interconnect layer comprising a plurality of interconnect paths connecting the semiconductor devices and embedded in a dielectric material; and a plurality of hard nanoparticles embedded in the dielectric material of the interconnect layer, the hard nanoparticles having a hardness greater than a hardness of the dielectric material and of a hardness of the interconnect paths.
1 . An integrated circuit die, comprising:
a device layer comprising a plurality of semiconductor devices;
an interconnect layer comprising a plurality of interconnect paths connecting the semiconductor devices and embedded in a dielectric material; and
a plurality of hard nanoparticles embedded in the dielectric material of the interconnect layer, the hard nanoparticles having a hardness greater than a hardness of the dielectric material and of a hardness of the interconnect paths.
2 . The integrated circuit die of claim 1 , wherein the plurality of hard nanoparticles embedded in the dielectric material have a plurality of different sizes, such that the hard nanoparticles are smaller than a distance between adjacent interconnect paths.
3 . The integrated circuit die of claim 2 , wherein the sizes are between 1 nm and 100 nm.
4 . The integrated circuit die of claim 1 , further comprising:
a sealing or overcoat layer over the interconnect layer, comprising a sealing or overcoat material; and
a second plurality of hard nanoparticles embedded in the sealing or overcoat layer, the second plurality of hard nanoparticles having a hardness greater than a hardness of the sealing or overcoat material.
5 . The integrated circuit die of claim 4 , wherein the second plurality of hard nanoparticles embedded in the dielectric material have a plurality of different sizes, such that the hard nanoparticles are larger than the distance between adjacent interconnect paths.
6 . The integrated circuit die of claim 5 , wherein the sizes of the second plurality of hard nanoparticles are between 100 nm and 10 μm.
7 . The integrated circuit die of claim 1 , wherein the hard nanoparticles comprise tungsten, diamond, or a carbide.
8 . The integrated circuit die of claim 1 , further comprising an x-ray blocking material having a mass attenuation coefficient below a predetermined noise threshold and having an x-ray attenuation coefficient above a predetermined attenuation threshold;
wherein the x-ray blocking material is disposed between the interconnect paths and an exterior of the integrated circuit die.
9 . The integrated circuit die of claim 8 , wherein the x-ray blocking material comprises a first layer of a first material having the mass attenuation coefficient below the predetermined noise threshold and a second layer of a second material having the x-ray attenuation coefficient above the predetermined attenuation threshold.
10 . The integrated circuit die of claim 9 , wherein the first material comprises aluminum and the second material comprises tungsten.
11 . The integrated circuit die of claim 8 , wherein the x-ray blocking material comprises a single layer of a single material having the mass attenuation coefficient below the predetermined noise threshold and having the x-ray attenuation coefficient above the predetermined attenuation threshold.
12 . The integrated circuit die of claim 11 , wherein the single material comprises tungsten.
13 . The integrated circuit die of claim 8 , wherein the x-ray blocking material comprises a coating on an uppermost coating layer.
14 . A method of manufacturing an integrated circuit die, comprising:
forming a device layer comprising a plurality of semiconductor devices;
forming an interconnect layer comprising a plurality of interconnect paths connecting the semiconductor devices and embedded in a dielectric material;
embedding a plurality of hard nanoparticles in the dielectric material of the interconnect layer, the hard nanoparticles having a hardness greater than a hardness of the dielectric material and of a hardness of the interconnect paths.
15 . The method of claim 14 , wherein the plurality of hard nanoparticles embedded in the dielectric material have a plurality of different sizes, such that the hard nanoparticles are smaller than a distance between adjacent interconnect paths.
16 . The method of claim 15 , wherein the sizes are between 1 nm and 100 nm.
17 . The method of claim 14 , further comprising:
depositing a sealing or overcoat layer over the interconnect layer, comprising a sealing or overcoat material; and
embedding a second plurality of hard nanoparticles in the sealing or overcoat layer, the second plurality of hard nanoparticles having a hardness greater than a hardness of the sealing or overcoat material.
18 . The method of claim 17 , wherein the second plurality of hard nanoparticles embedded in the dielectric material have a plurality of different sizes, such that the hard nanoparticles are larger than the distance between adjacent interconnect paths.
19 . The method of claim 18 , wherein the sizes of the second plurality of hard nanoparticles are between 100 nm and 10 μm.
20 . The method of claim 14 , wherein the hard nanoparticles comprise tungsten, diamond, or a carbide.
21 . The method of claim 14 , further comprising disposing an x-ray blocking material between the interconnect paths and an exterior of the integrated circuit die, the x-ray blocking material having a mass attenuation coefficient below a predetermined noise threshold and having an x-ray attenuation coefficient above a predetermined attenuation threshold.
22 . The method of claim 21 , wherein the x-ray blocking material comprises a first layer of a first material having the mass attenuation coefficient below the predetermined noise threshold and a second layer of a second material having the x-ray attenuation coefficient above the predetermined attenuation threshold.
23 . The method of claim 22 , wherein the first material comprises aluminum and the second material comprises tungsten.
24 . The method of claim 21 , wherein the x-ray blocking material comprises a single layer of a single material having the mass attenuation coefficient below the predetermined noise threshold and having the x-ray attenuation coefficient above the predetermined attenuation threshold.
25 . The method of claim 24 , wherein the single material comprises tungsten.
26 . The method of claim 21 wherein the x-ray blocking material comprises a coating on an uppermost coating layer.
27 . An integrated circuit, comprising:
a package;
an integrated circuit die within the package, the integrated circuit die comprising:
a device layer comprising a plurality of semiconductor devices;
an interconnect layer comprising a plurality of interconnect paths connecting the semiconductor devices and embedded in a dielectric material; and
a plurality of hard nanoparticles embedded in the dielectric material of the interconnect layer, the hard nanoparticles having a hardness greater than a hardness of the dielectric material and of a hardness of the interconnect paths.
28 . The integrated circuit of claim 27 , wherein the plurality of hard nanoparticles embedded in the dielectric material have a plurality of different sizes, such that the hard nanoparticles are smaller than a distance between adjacent interconnect paths.
29 . The integrated circuit of claim 27 , the integrated circuit die further comprising:
a sealing or overcoat layer over the interconnect layer, comprising a sealing or overcoat material; and
a second plurality of hard nanoparticles embedded in the sealing or overcoat layer, the second plurality of hard nanoparticles having a hardness greater than a hardness of the sealing or overcoat material.
30 . The integrated circuit of claim 29 , wherein the second plurality of hard nanoparticles embedded in the dielectric material have a plurality of different sizes, such that the hard nanoparticles are larger than the distance between adjacent interconnect paths.
31 . The integrated circuit of claim 27 , the integrated circuit die further comprising:
an x-ray blocking material having a mass attenuation coefficient below a predetermined noise threshold and having an x-ray attenuation coefficient above a predetermined attenuation threshold;
wherein the x-ray blocking material is disposed between the interconnect paths and an exterior of the integrated circuit die.
32 . The integrated circuit of claim 28 , wherein the x-ray blocking material comprises a first layer of a first material having the mass attenuation coefficient below the predetermined noise threshold and a second layer of a second material having the x-ray attenuation coefficient above the predetermined attenuation threshold.
33 . The integrated circuit of claim 28 , wherein the x-ray blocking material comprises a single layer of a single material having the mass attenuation coefficient below the predetermined noise threshold and having the x-ray attenuation coefficient above the predetermined attenuation threshold.