Reflective mask blank for EUV lithography and reflective mask for EUV lithography
View Patent ↗To provide an EUV mask of which a decrease in the contrast of reflected light at the mask pattern boundary, particularly a decrease in the contrast of reflected light at the boundary on the mask pattern outer edge, is suppressed, and an EUV mask blank to be used for production of the EUV mask. A reflective mask blank for EUV lithography, comprising: a substrate, and a reflective layer to reflect EUV light, and an absorber layer to absorb EUV light, formed in this order over the substrate, a step on at least a part of the substrate being provided between a first portion where the absorber layer is removed at the time of patterning, and a second portion where the absorber layer is not removed at the time of patterning, adjacent to the first portion where the absorber layer is removed.
1. A reflective mask blank for EUV lithography, comprising:
a substrate;
a reflective layer formed over the substrate and configured to reflect EUV light; and
an absorber layer formed over the reflective layer and configured to absorb EUV light,
wherein the reflective layer has a step portion forming a boundary between a first portion of the substrate where the absorber layer is removed at the time of patterning, and a second portion of the substrate where the absorber layer is not removed at the time of patterning, and the second portion of the substrate is adjacent to the first portion of the substrate.
2. The reflective mask blank for EUV lithography according to claim 1 , wherein the step portion of the reflective layer has an edge which is on a side of the first portion than a boundary between the first portion and the second portion.
3. A reflective mask blank for EUV lithography, comprising:
a substrate;
a reflective layer formed over the substrate and configured to reflect EUV light; and
an absorber layer formed over the reflective layer and configured to absorb EUV light,
wherein the reflective layer has a step portion forming a boundary between a first portion of the substrate where the absorber layer is removed at the time of patterning, and a second portion of the substrate where the absorber layer is not removed at the time of patterning, the second portion of the substrate is adjacent to the first portion of the substrate, and the first portion of the substrate is configured to form an outer edge of a mask pattern.
4. The reflective mask blank for EUV lithography according to claim 3 , wherein the step portion of the reflective layer has an edge which is on a side of the first portion than a boundary between the first portion and the second portion.
5. The reflective mask blank for EUV lithography according to claim 2 , wherein a distance L between the edge of the step portion and a boundary of a mask pattern satisfies L=(t+h)×tan α−h, where α (°) is an incidence angle of the EUV light to an EUV mask, t (mm) is a thickness of the absorber layer, and h (nm) is a height of the step portion.
6. The reflective mask blank for EUV lithography according to claim 1 , wherein the step portion of the reflective layer has a height which is in a range of from 2 to 10 nm.
7. The reflective mask blank for EUV lithography according to claim 1 , wherein the substrate has a thin film formed on a portion of a surface of the substrate, and the step portion of the reflective layer is formed by the thin film.
8. The reflective mask blank for EUV lithography according to claim 1 , wherein the substrate has a portion formed by removing a part of the substrate, and the step portion of the reflective layer is formed by the portion of the substrate.
9. The reflective mask blank for EUV lithography according to claim 1 , wherein a low reflective layer against an inspection light to be used for inspection of a mask pattern is formed on the absorber layer.
10. The reflective mask blank for EUV lithography according to claim 1 , further comprising a protective layer configured to protect the reflective layer and formed between the reflective layer and the absorber layer.
11. The reflective mask blank for EUV lithography according to claim 1 , further comprising a positioning mark formed on an outside of an exposure region.
12. A reflective mask for EUV lithography formed by patterning the reflective mask blank for EUV lithography as defined in claim 1 .
13. A process for producing a semiconductor integrated circuit, comprising:
exposing an object using the reflective mask for EUV lithography as defined in claim 12 such that a semiconductor integrated circuit is formed on the object.