Systems and methods for processing memory requests in a multi-processor system using a probe engine

1. A processing system, comprising:

a first processing unit configured to receive a request to access a memory word and to determine whether the requested memory word is stored in a local memory of the first processing unit; and

the first processing unit configured to store a list of all addresses of the local memory that are cached in a cache of the first processing unit, cached in a remote memory of a second processing unit, and cached in any other component of the processing system, and send a memory probe to the second processing unit to determine whether the remote memory of the second processing unit holds the requested memory word in a cache line with a value that is different from a value stored in the local memory of the first processing unit, wherein the memory probe is sent when there is a match for the requested memory word in the stored list of all addresses.

2. The processing system of claim 1 , wherein the first processing unit is a graphics processing unit (GPU) and the second processing unit is a central processing unit (CPU).

3. The processing system of claim 1 , wherein the second processing unit comprises an address processing unit, wherein an execution engine of the second processing unit is configured to generate a memory request, and wherein the address processing unit is configured to use a routing table to determine a location of the memory word associated with the memory request.

4. The processing system of claim 1 , wherein the first processing unit comprises a probe engine and a probe filter, and wherein the probe engine is configured to transmit the memory probe in response to the probe filter indicating that the requested memory word is cached in another cache of the second processing unit.

5. The processing system of claim 1 , wherein the cache of the first processing unit is virtually tagged and the second processing unit comprises another cache that is physically tagged, wherein the first processing unit further comprises a reverse lookup table configured to translate a received physical memory address to a virtual memory address.

6. The processing system of claim 2 , wherein the cache of the first processing unit includes a first portion and a second portion, wherein the first portion of the cache is configured to cache memory words located in the local memory, and wherein the first portion is physically tagged.

7. The processing system of claim 6 , wherein the second portion of the cache is virtually tagged.

8. A method of processing a memory request in a processing system, comprising:

receiving a request, by a first processing unit, to access a memory word;

determining whether the requested memory word is stored in a local memory of the first processing unit;

storing a list of all addresses of the local memory that are cached in a cache of the first processing unit, cached in a remote memory of a second processing unit, and cached in any other component of the processing system; and

when there is a match for the requested memory word in the stored list of all addresses, sending a memory probe to the second processing unit to determine whether the remote memory of the second processing unit holds the requested memory word in a cache line with a value that is different from a value stored in the local memory of the first processing unit.

9. The method of claim 8 , wherein a probe filter maintains the list of all addresses of the first processing unit that are cached in the remote memory of the second processing unit and any other component of the processing, system.

10. The method of claim 8 , further comprising:

determining that the cache of the first processing unit cannot service the memory request.

11. The method of claim 8 , further comprising:

translating a memory address of the requested memory word included in the probe from a physical address to a virtual address.

12. A non-transitory computer readable medium carrying one or more sequences of one or more instructions for execution by one or more processors to perform a method for processing a memory request in a processing system, the instructions when executed by the one or more processors, cause the one or more processors to:

receive a request, by a first processing unit, to access a memory word;

determine whether the requested memory word is stored in a local memory of the first processing unit;

store a list of all addresses of the local memory that are cached in a cache of the first processing unit, cached in a remote memory of a second processing unit, and cached in any other component of the processing system; and

send a memory probe to the second processing unit to determine whether the remote memory of the second processing unit holds the requested memory word in a cache line with a value that is different from a value stored in the local memory of the first processing unit, wherein the memory probe is sent when there is a match for the requested memory word in the stored list of all addresses.

13. The computer readable medium of claim 12 , wherein a probe filter maintains the list of all addresses of the first processing unit that are cached in the remote memory of the second processing unit and any other component of the processing system.

14. The computer readable medium of claim 12 , the instructions when executed by the one or more processors further cause the one or more processors to:

determine that the cache of the first processing unit cannot service the memory request.