Summer block for a decision feedback equalizer

1. A Decision Feedback Equalizer (DFE) comprising:

a Feed Forward Equalizer (FFE) configured to process an unequalized data signal to provide a FFE data signal;

a Feedback Equalizer (FBE) configured to process a decision data signal to provide a FBE data signal;

a loop unrolling device configured to add a direct current (DC) offset, using a summer block, to a combination of the FFE data signal and the FBE data signal to provide an offset data signal and to process the offset data signal to provide an equalized data signal, wherein the DC offset is determined based on:

a FBE tap weight value, and

at least one of a vertical eye asymmetry in the unequalized data signal and parameter mismatches of devices used to implement the DFE; and

a decision device configured to process the equalized data signal to provide the decision data signal.

2. The DFE of claim 1 , wherein the devices comprise transistors and the parameter mismatches comprise at least one of a mismatch between threshold voltages of the devices, a mismatch between charge carrier mobility, a mismatch between gate oxide capacitance, a mismatch between channel lengths of the devices, and a mismatch between channel widths of the devices.

3. The DFE of claim 1 , wherein the devices comprise resistors and the parameter mismatches comprise a mismatch in resistance values associated with the resistors.

4. The DFE of claim 1 , wherein the summer block comprises:

a gain stage configured to amplify the combination of the FFE data signal and the FBE data signal to provide an amplified version of the combination of the FFE data signal and the FBE data signal at an output: and

a summing stage configured to add the DC offset to the amplified version of the combination of the FFE data signal and the FBE data signal to provide the offset data signal.

5. The DFE of claim 4 , wherein the gain stage is a current-mode logic buffer.

6. The DFE of claim 4 , wherein the summing stage includes a plurality of current sources and is configured to couple one or more of the plurality of current sources to the output of the gain stage to add the DC offset.

7. The DFE of claim 1 , wherein the summer block adds the DC offset to the combination of the FFE data signal and the FBE data signal by adjusting a threshold level of a slicer within the loop unrolling device.

8. A Decision Feedback Equalizer (DFE) comprising:

a loop unrolling device configured to add a direct current (DC) offset, using a summer block, to an unequalized data signal received over a channel to provide an offset data signal and to process the offset data signal to provide an equalized data signal, wherein the DC offset is determined based on:

a Feedback Equalizer (FBE) tap weight value, and

at least one of a vertical eye asymmetry in the unequalized data signal and parameter mismatches of devices used to implement the DFE; and

a decision device configured to process the equalized data signal to provide a decision data signal.

9. The DFE of claim 8 , wherein the devices comprise transistors and the parameter mismatches comprise at least one of a mismatch between threshold voltages of the devices, a mismatch between charge carrier mobility, a mismatch between gate oxide capacitance, a mismatch between channel lengths of the devices, and a mismatch between channel widths of the devices.

10. The DFE of claim 8 , wherein the devices comprise resistors and if e parameter mismatches comprise a mismatch in resistance values associated with the resistors.

11. The DFE of claim 8 , wherein the summer block comprises:

a gain stage configured to amplify the unequalized data signal to provide an amplified version of the unequalized data signal at an output; and

a summing stage configured to add the DC offset to the amplified version of the unequalized data signal to provide the offset data signal.

12. The DFE of claim 11 , wherein the gain stage is a current-mode logic buffer.

13. The DFE of claim 11 , wherein the summing stage includes a plurality of current sources and is configured to couple one or more of the plurality of current sources to the output of the gain stage to add the DC offset.

14. The DFE of claim 8 , wherein the summer block adds the DC offset to the unequalized data signal by adjusting a threshold level of a slicer within the loop unrolling device.

15. A summer block implemented in a Decision Feedback Equalizer (DFE), the summer block configured to add a direct current (DC) offset to a data signal received over a channel, the summer block comprising:

a gain stage configured to amplify the data signal to provide an amplified version of the data signal at an output; and

a summing stage configured to add the DC offset to the amplified version of the data signal to provide an offset data signal, wherein the DC offset is determined based on:

a Feedback Equalizer tap weight value, and

at least one of a vertical eye asymmetry in the data signal and parameter mismatches of devices used to implement the DFE.

16. The summer block of claim 15 , wherein the devices comprise transistors and the parameter mismatches comprise at least one of a mismatch between threshold voltages of the devices, a mismatch between charge carrier mobility, a mismatch between gate oxide capacitance, a mismatch between channel lengths of the devices, and a mismatch between channel widths of the devices.

17. The summer block of claim 15 , wherein the devices comprise resistors and the parameter mismatches comprise a mismatch in resistance values associated with the resistors.