Proper frequency planning in a synthetic instrument RF system

1. A method of clocking an analog-to-digital converter (ADC) in a synthetic instrument unit comprising:

amplifying an input clock to an amplifier to produce an amplified clock;

filtering the amplified clock to produce a filtered clock;

clocking the ADC of the synthetic instrument unit with the filtered clock, wherein the ADC samples input data at a sampling frequency, wherein the input data is received at the ADC at an input frequency corresponding to an intermediate frequency (IF) signal; and

switching the filtered clock off a clock path of the ADC when the ADC is not sampling input data.

2. The method of claim 1 wherein the filtering further comprises:

filtering the amplified clock with a narrow bandpass filter.

3. The method of claim 1 wherein the filtering further comprises:

filtering the amplified clock with at least a second order narrowband filter.

4. The method of claim 1 wherein clocking the ADC further comprises:

clocking the ADC that is an ADC formed with integrated circuits in a silicon chip.

5. The method of claim 4 wherein amplifying the input clock further comprises:

amplifying the input clock that is received externally from the chip.

6. The method of claim 1 wherein the input frequency of the ADC is a second or higher Nyquist zone that is above the sampling frequency of the ADC.

7. The method of claim 1 further comprising:

selecting a center IF of the input data, wherein the ADC is to sample the input data at the center IF; and

selecting the input clock based, at least in part, on the center IF.

8. The method of claim 1 further comprising:

determining if the dynamic range (DR) of the IF signal is within a DR window; and

adjusting the IF signal when the DR is not within the DR window to produce the updated IF signal.

9. A method for frequency planning a synthetic instrument system comprising:

selecting an intermediate frequency (IF) of an input data;

determining if a system bandwidth (BW) is above a tolerance at the IF;

adjusting the IF when the system BW is not the above the tolerance to produce an updated IF;

selecting an analog-to-digital converter (ADC) sampling clock frequency of an ADC sampling clock based, at least in part, on the updated IF; and

selecting a bandpass filter to filter the ADC sampling clock based, at least in part, on the ADC sampling clock frequency.

10. The method for frequency planning of claim 9 further comprising:

selecting an amplifier to amplify the ADC sampling clock prior to filtering the ADC sampling clock.

11. The method for frequency planning of claim 9 further comprising:

selecting an ADC based on the updated IF, wherein the ADC is to filter the input data based on the ADC sampling clock frequency.

12. The method for frequency planning of claim 9 further comprising:

determining if a BW of the ADC is within a BW window; and

adjusting the IF when the BW of the ADC is not within the BW window to produce the updated IF.

13. The method for frequency planning of claim 12 wherein the determining if the BW of the ADC is within a BW window is performed after the selecting an intermediate IF.

14. The method for frequency planning of claim 9 further comprising:

determining if the dynamic range (DR) of the input data is within a DR window; and

adjusting the IF when the DR of the input data is not within the DR window to produce the updated IF.

15. The method for frequency planning of claim 9 further comprising:

selecting the filter for filtering the ADC sampling clock prior to sampling the updated IF with an ADC.

16. The method for frequency planning of claim 9 wherein the selecting the filter further comprises:

selecting a narrowband bandpass filter to filter the ADC sampling clock.

17. The method for frequency planning of claim 9 wherein selecting the IF and selecting the ADC sampling clock further comprises:

selecting the IF and the ADC sampling clock so that the IF has a frequency that is about four times greater than the ADC sampling clock frequency.

18. The method for frequency planning of claim 9 further comprising:

selecting an ADC based on the updated IF, wherein the ADC is to filter the input data based on the ADC sampling clock frequency; and

implementing the ADC and the bandpass filter in one or more silicon chips mounted on a printed circuit board.

19. A synthetic instrument logic comprising:

an analog-to-digital converter (ADC) configured to digitally sample input data at an intermediate frequency (IF);

an amplifier configured to amplify an input clock to create an amplified clock;

a narrow bandpass filter configured to filter the amplified clock to create a filtered clock with a frequency corresponding to the frequency of the input, wherein the filtered clock is used to clock the ADC, wherein the amplified clock is filtered before being input to the ADC;

switch logic configured to connect the filtered clock to the ADC and to disconnect the filtered clock to the ADC; and

control logic configured to control the switching logic to connect the filter clock to the ADC when the ADC is to sample the input data and to disconnect the filter clock from the ADC when there is no input data to sample.

20. The synthetic instrument logic of claim 19 wherein the ADC further comprises:

an input frequency, wherein the input frequency is in a Nyquist zone above the frequency of filtered clock.