Apparatus and method for programmable read preamble with training pattern

1. A memory device, comprising:

a preamble memory that is arranged to store a read preamble such that the read preamble includes two training patterns that are suitable for:

aligning a capture point for read data on two communication lines; and

determining a period of time within a clock cycle the read data is simultaneously available on the two communication lines,

wherein the training patterns can be altered at least once subsequent to manufacture of the preamble memory, wherein the preamble memory is configured such that the read preamble is programmable during power up, and further configured such the read preamble is locked after power up is complete; and

a memory controller that is configured, in response to a read command, to:

provide the read preamble stored in the preamble memory; and

provide the read data.

2. The memory device of claim 1 , wherein

the preamble memory is further arranged such that a bit length of one of the two training patterns is programmable such that the bit length of the one of the two training patterns can be altered at least once subsequent to the manufacture of the preamble memory.

3. The memory device of claim 1 , wherein

the memory controller is configured to provide the read data on the two communication lines in a bus immediately after a plurality of dummy clock cycles, and to provide the read preamble on the two communication lines in the bus during at least a portion of the plurality of dummy clock cycles.

4. The memory device of claim 1 , wherein

the preamble memory includes means for programming the read preamble, or

the memory controller includes means for providing the read preamble stored in the preamble memory responsive to the read command.

5. The memory device of claim 1 , wherein

the preamble memory is non-volatile memory.

6. The memory device of claim 5 , wherein

the preamble memory is flash memory.

7. The memory device of claim 5 , wherein

the memory controller is configured to lock the read preamble after the read preamble is programmed.

8. The memory device of claim 1 , wherein

the preamble memory is volatile memory.

9. The memory device of claim 8 , wherein

the preamble memory is random access memory.

10. The memory device of claim 1 , further comprising:

a backup preamble memory that is arranged to store a default read preamble.

11. A memory device, comprising:

a preamble memory that is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data, wherein the training pattern can be altered at least once subsequent to manufacture of the preamble memory;

a memory controller that is configured to perform actions, including:

in response to a read command:

providing the read preamble stored in the preamble memory; and

providing the read data; and

a backup preamble memory that is arranged to store a default read preamble, wherein

the backup preamble memory is non-volatile memory, the preamble memory is volatile memory, the preamble memory stores the default read preamble from the backup preamble memory as the read preamble at power up of the memory device, and wherein the read preamble can be altered at least once subsequent to manufacture of the preamble memory after power up of the memory device.

12. The memory device of claim 11 , wherein the backup preamble memory is configured such that the default read preamble is programmable such that the backup read preamble can be altered at least once subsequent to manufacture of the backup preamble memory.

13. The memory device of claim 11 , wherein the backup preamble memory is flash memory.

14. The memory device of claim 11 , wherein the preamble memory is random access memory.

15. A method, comprising:

storing a read preamble in a device such that the read preamble includes two training patterns that are suitable for:

aligning a capture point for read data on two communication lines; and

determining a period of time within a clock cycle the read data is simultaneously available on the two communication lines, wherein the read preamble is programmable during power up and the read preamble is locked after power up is complete;

altering the read preamble subsequent to manufacture of the device; and

in response to a read command:

providing the read preamble stored in the preamble memory; and

providing the read data.

16. The method of claim 15 , further comprising:

adjusting a bit length of one of the training pattern at least once subsequent to the manufacture of the device.

17. A system, including:

a data capturing device that is configured to:

provide a read command;

receive a response to the read command; and

employ a read preamble to align a capture point for read data on two communication lines and determine a period of time within a clock cycle the read data is simultaneously available on the two communication lines; and

a memory device that is configured to:

store the read preamble such that the read preamble includes two training patterns that are suitable for:

aligning the capture point for the read data on the two communication lines; and

determining the period of time the read data is available on the two communication lines, wherein at least one of the two training patterns can be altered at least once subsequent to manufacture of the memory device, and wherein the read preamble is programmable during power up and the read preamble is locked after power up is complete; and

in response to the read command:

provide the read preamble stored in the memory device; and

provide the read data.

18. The system of claim 17 , wherein

the memory device is further arranged such that a bit length of one of the training patterns is programmable such that the bit length of the one of the two training patterns can be altered at least once subsequent to the manufacture of the memory device.