Apparatus, method, and manufacture for using a read preamble to optimize data capture
View Patent ↗A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern.
1. A memory device, comprising:
a memory; and
a memory controller configured to:
in response to a burst read command that includes a target address, provide, to first and second data lines, data stored in the memory at the target address after a plurality of dummy clock cycles; and
provide first and second preambles on the first and second data lines, respectively, during at least a portion of the plurality of dummy clock cycles such that the first and second preambles comprises first and second data training patterns, respectively;
wherein the first and second data training patterns are designed to be used to determine a period of time that valid data is concurrently available on the first and second data lines, and wherein the period of time comprises a minimum period of time during a clock cycle for data capture; and
wherein each of the first and second preambles comprises: 1) at least one 0 to 1 and 1 to 0 transition on both the first and second data lines; 2) at least one 0 to 1 transition on the first data line concurrently with a 1 to 0 transition on the second data line; and 3) at least one 1 to 0 transition on the first data line concurrently with a 0 to 1 transition on the second data line.
2. The memory device of claim 1 , wherein the memory controller is configured to provide the first and second preambles on the first and second data lines during the at least the portion of the plurality of dummy clock cycles.
3. The memory device of claim 1 , wherein:
the memory controller is further configured to provide the first and second data training patterns to a host controller prior to the burst read commend.
4. The memory device of claim 1 , wherein the memory comprises a flash memory.
5. The memory device of claim 1 , wherein at least one of the first and second data lines is a serial data line.
6. The memory device of claim 1 , wherein at least one of the first and second data lines is a Serial Peripheral Interface (SPI) bus.
7. The memory device of claim 1 , wherein the memory controller is configured to provide the first and second preambles in response to the burst read command received by the memory controller.
8. The memory device of claim 1 , wherein each of the first and second preambles further comprises: 4) at least one 0 to 0 and 1 to 1 transition on both the first and second data lines.
9. A data capturing device, comprising:
a data capturing component; and
a data capturing device controller configured to:
provide a burst read command to a memory system;
receive, on a bus, a response to the burst read command from the memory system comprising first and second data lines, wherein the first and second data lines include first and second preambles, respectively, and memory system data stored in the memory system, and wherein the first and second preambles comprise first and second data training patterns, respectively;
wherein each of the first and second preambles comprises: 1) at least one 0 to 1 and 1 to 0 transition on both the first and second data lines; 2) at least one 0 to 1 transition on the first data line concurrently with a 1 to 0 transition on the second data line; and 3) at least one 1 to 0 transition on the first data line concurrently with a 0 to 1 transition on the second data line;
employ the first and second preambles and the first and second data training patterns to control the data capturing component to align a capture point of the memory system data with the memory system data; and
determine a period of time that valid data is concurrently available on both the first and second data lines using the expected first and second training patterns, wherein the period of time comprises a minimum period of time during a clock cycle for data capture.
10. A method, comprising:
in response to a burst read command that includes a target address, providing, to first and second data lines, data stored in a memory at the target address after a plurality of dummy clock cycles; and
providing first and second preambles on the first and second data lines, respectively, during at least a portion of the plurality of dummy clock cycles such that the first and second preambles comprises first and second data training patterns, respectively;
wherein the first and second data training patterns are designed to be used to determine a period of time that valid data is concurrently available on the first and second data lines, and wherein the period of time comprises a minimum period of time during a clock cycle for data capture; and
wherein each of the first and second preambles comprises: 1) at least one 0 to 1 and 1 to 0 transition on both the first and second data lines; 2) at least one 0 to 1 transition on the first data line concurrently with a 1 to 0 transition on the second data line; and 3) at least one 1 to 0 transition on the first data line concurrently with a 0 to 1 transition on the second data line.
11. The method of claim 10 , wherein:
at least one data line of the first and second data lines includes a plurality of serial data lines; and
wherein providing the first and second preambles comprises providing the first or second preamble on each of the plurality of serial data lines during the at least the portion of the plurality of dummy clock cycles.
12. The method of claim 10 , wherein the providing comprises providing the first and second preambles in response to the burst read command.
13. A manufacture including a non-transitory processor-readable storage medium having processor-executable code encoded therein, which, when executed by one or more processors, is configured to:
in response to a burst read command that comprises a target address, provide, to first and second data lines, data stored in the memory at the target address after a plurality of dummy clock cycles; and
provide first and second preambles on the first and second data lines, respectively, during at least a portion of the plurality of dummy clock cycles such that the first and second preambles comprises first and second data training patterns, respectively;
wherein the first and second data training patterns are designed to be used to determine a period of time that valid data is concurrently available on the first and second data lines, and wherein the period of time comprises a minimum period of time during a clock cycle for data capture; and
wherein each of the first and second preambles comprises: 1) at least one 0 to 1 and 1 to 0 transition on both the first and second data lines; 2) at least one 0 to 1 transition on the first data line concurrently with a 1 to 0 transition on the second data line; and 3) at least one 1 to 0 transition on the first data line concurrently with a 0 to 1 transition on the second data line.
14. The manufacture of claim 13 , wherein the non-transitory processor-readable storage medium further includes processor-executable code encoded therein, which, when executed by the one or more processors is configured to provide the first and second preambles in response to the burst read command.
15. A system comprising:
a data capturing device that is configured to:
provide a burst read command;
receive a response to the burst read command on first and second data lines, wherein the response comprises first and second preambles on the first and second data line, respectively, and memory system data, and wherein the first and second preambles include first and second data training patterns, respectively;
wherein each of the first and second preambles comprises: 1) at least one 0 to 1 and 1 to 0 transition on both the first and second data lines; 2) at least one0 to 1 transition on the first data line concurrently with a 1 to 0 transition on the second data line; and 3) at least one 1 to 0 transition on the first data line concurrently with a 0 to 1 transition on the second data line;
employ the first and second preambles and the first and second data training patterns to align a capture point for memory controller data with the memory system data; and
determine a period of time that valid data is concurrently available on both the first and second data lines using the first and second data training patterns, wherein the period of time comprises a minimum period of time during a clock cycle for data capture; and
a memory controller that is configured to provide the response to the burst read command to the first and second data lines such that the response comprises the first and second preambles and the memory system data, wherein the memory controller is configured to provide the memory system data during a plurality of dummy clock cycles, and to provide the first and second preambles on the first and second data lines, respectively, during at least a portion of the plurality of dummy clock cycles.
16. The system of claim 15 , wherein the data capturing device comprises a host controller.
17. The system of claim 15 , wherein the system is an embedded system.
18. The system of claim 15 , wherein the memory controller is configured to provide the first and second preambles in response to the burst read command received by the memory controller.
19. A manufacture comprising:
one or more processors; and
random access memory having processor-executable code encoded thereon which, when executed by the one or more processors, is configured to:
in response to a burst read command that comprises a target address, provide, to first and second data lines, data stored in the memory at the target address after a plurality of dummy clock cycles; and
provide first and second preambles on the first and second data lines, respectively, during at least a portion of the plurality of dummy clock cycles such that the first and second preambles include first and second data training patterns, respectively;
wherein the first and second data training patterns are designed to be used to determine a period of time that valid data is concurrently available on both the first and second data lines, and wherein the period of time comprises a minimum period of time during a clock cycle for data capture; and
wherein each of the first and second preambles comprises: 1) at least one 0 to 1 and 1 to 0 transition on both the first and second data lines; 2) at least one 0 to 1 transition on the first data line concurrently with a 1 to 0 transition on the second data line; and 3) at least one 1 to 0 transition on the first data line concurrently with a 0 to 1 transition on the second data line.