Method for forming bit lines for semiconductor devices
View Patent ↗A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.
1. A method for forming a semiconductor device, the method comprising:
forming a plurality of memory cells, including:
forming a first dielectric layer over a first portion of a substrate,
forming a charge storage layer over the first dielectric layer, and
forming masks over portions of the first dielectric layer and the charge storage layer; and
forming a plurality of bit lines, each of the bit lines acting as a source region or a drain region for a portion of the plurality of memory cells, where forming the plurality of bit lines comprises:
etching a trench in the charge storage layer and the first dielectric layer, the trench extending to the substrate, where the masks prevent removal of portions of the first dielectric layer and the charge storage layer during etching of the trench,
after etching the trench, implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width, where implanting the n-type impurities includes removing a portion of the masks to cause the first width of the n-type region to be greater than a width of the trench, and
implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width, where the second depth is greater than the first depth and the second width is greater than the first width.
2. The method of claim 1 , where the first width ranges from about 1100 Å to about 1700 Å.
3. The method of claim 1 , where the second width ranges from about 1200 Å to about 2000 Å.
4. The method of claim 1 , where implanting the n-type impurities comprises performing a vertical implantation having no tilt angle; and
where implanting the p-type impurities comprises implanting the p-type impurities using a tilt angle ranging from about 10 degrees to 20 degrees.
5. The method of claim 1 , where implanting the p-type impurities comprises:
performing a first implantation to form a first portion of the p-type region, and
performing a second implantation to form a second portion of the p-type region.
6. The method of claim 1 , where the first depth ranges from 200 Å to 400 Å below an upper surface of the substrate and the second depth ranges from 300 Å to 1000 Å below the upper surface of the substrate.
7. The method of claim 1 , where implanting the n-type impurities comprises using a first energy implantation to implant the n-type impurities, where the first energy implantation is higher than a second energy implantation used to implant the p-type impurities.
8. The method of claim 1 , where implanting the n-type impurities comprises implanting n-type impurities at a first implantation dosage and implanting the p-type impurities comprises implanting p-type impurities at a second implantation dosage, the first implantation dosage being greater than the second implantation dosage.
9. The method of claim 1 , where forming the second dielectric layer comprises:
forming a high dielectric constant layer comprising aluminum or hafnium.
10. The method of claim 1 , where forming the charge storage layer comprises:
depositing a nitride layer.
11. The method of claim 1 , where implanting the n-type impurities comprises performing an implantation having substantially no tilt angle; and
where implanting the p-type impurities comprises:
performing a first implantation at a first tilt angle to form a first portion of the p-type region, and
performing a second implantation at a second tilt angle to form a remaining portion of the p-type region.
12. The method of claim 1 , where the second width ranges from about 100 Å to 300 Å greater than the first width.
13. The method of claim 1 , where a lower portion of the p-type region is formed at a depth ranging from about 100 Å to about 800 Å below a lower portion of the n-type region.
14. A method, comprising:
forming a plurality of memory cells, including:
forming a first dielectric layer over a first portion of a substrate,
forming a charge storage layer over the first dielectric layer, and
forming masks over portions of the first dielectric layer and the charge storage layer; and
forming a plurality of bit lines, each of the bit lines acting as a source region or a drain region for a portion of the plurality of memory cells, where forming the plurality of bit lines comprises:
etching a trench through the charge storage layer and the first dielectric layer to the substrate, where the masks prevent removal of portions of the first dielectric layer and the charge storage layer during etching of the trench,
after etching the trench, implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width, where implanting the n-type impurities includes removing a portion of the masks to cause the first width of the n-type region to be greater than a width of the trench,
implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width,
forming a second dielectric layer over the charge storage layer, and
forming a control gate over the second dielectric layer.
15. The method of claim 14 , where the second depth ranges from about 100 Å to about 800 Å more than the first depth.
16. The method of claim 14 where the second width ranges from about 100 Å to about 200 Å more than the first width.
17. The method of claim 14 , where the first depth ranges from about 200 Å to about 400 Å below an upper surface of the substrate, the first width ranges from about 1100 Å to about 1700 Å, the second depth ranges from about 300 Å to about 1000 Å below the upper surface of the substrate, and the second width ranges from about 1200 Å to about 2000 Å.
18. The method of claim 14 , where the n-type impurities are implanted using a higher energy implantation and a higher dosage concentration than the p-type impurities.
19. The method of claim 14 , where forming the second dielectric layer comprises:
forming a high dielectric constant layer comprising at least one of aluminum or hafnium.
20. The method of claim 14 , where forming the charge storage layer comprises:
depositing a nitride layer.