THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE
A semiconductor structure includes an interconnect region and a semiconductor stack bonded to the interconnect region through a bonding region. The stack includes two semiconductor layers having different electrical properties. The stack also includes single crystalline semiconductor material. The stack can be processed to form a mesa structure and the mesa structure can be processed to from a vertically oriented semiconductor device.
1 . An apparatus, comprising:
an interconnect region; and
a multilayer semiconductor structure bonded to the interconnect region with a bonding region, the structure including two semiconductor regions having different electrical properties.
2 . The apparatus of claim 1 , wherein the structure includes a cleaved surface.
3 . The apparatus of claim 1 , wherein the structure includes a planarized surface.
4 . The apparatus of claim 1 , wherein the structure includes a planarized surface facing the bonding region.
5 . The apparatus of claim 1 , wherein the bonding region includes a metal layer bonded to a semiconductor layer.
6 . The apparatus of claim 1 , wherein the structure includes single crystalline semiconductor material.
7 . The apparatus of claim 1 , wherein the two semiconductor regions have opposite conductivity types.
8 . The apparatus of claim 1 , wherein the two semiconductor regions have the same conductivity type.
9 . The apparatus of claim 1 , wherein the structure includes a sidewall which extends between a surface and an opposed surface of the structure.
10 . The apparatus of claim 1 , wherein the structure includes an etched sidewall which extends between a surface and an opposed surface of the structure.
11 . An apparatus, comprising:
an interconnect region having a conductive line;
a bonding region connected to the conductive line; and
a semiconductor structure coupled to the interconnect region with the bonding region, the structure including a planarized surface which faces the bonding region.
12 . The apparatus of claim 11 , wherein the bonding region includes a metal layer.
13 . The apparatus of claim 11 , wherein the structure includes two semiconductor regions having different electrical properties.
14 . The apparatus of claim 11 , wherein the structure includes a pn junction.
15 . The apparatus of claim 11 , wherein the bonding region establishes a bonding interface with the structure.
16 . The apparatus of claim 11 , further including a control dielectric adjacent to a sidewall of the structure.
17 . The apparatus of claim 11 , further including a control terminal, wherein the conductivity of the material of the structure is adjustable in response to adjusting a signal provided to the control terminal.
18 . The apparatus of claim 11 , further including a control terminal, wherein a current flow through the bonding region is adjustable in response to adjusting a signal provided to the control terminal.
19 . The method of claim 11 , wherein the bonding region covers a major surface of the interconnect region.
20 . An apparatus, comprising:
an interconnect region; and
a multilayer semiconductor structure which includes first and second semiconductor layers having different electrical properties; and
a bonding region which couples the structure to the interconnect region through a bonding interface, wherein the structure includes a first planarized surface positioned proximate to the bonding region.
21 . The apparatus of claim 20 , wherein the structure consists essentially of blanket layers of semiconductor material.
22 . The apparatus of claim 21 , wherein the structure consists essentially of single crystal semiconductor material.
23 . The apparatus of claim 22 , further including a pn junction proximate to an interface between the first and second semiconductor layers.
24 . The apparatus of claim 23 , wherein the structure includes a second planarized surface, the pn junction being between the first and second planarized surfaces.