IP Library Granted Patent US 8,402,217
Granted Patent B2
US 8,402,217 · App. 12/881,881 · Granted Mar 19, 2013

Implementing RAID in solid state memory

Inventor: Gregory Burd (San Jose, CA)
Assignee: Marvell International Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,402,217
App. No.
12/881,881
Granted
Mar 19, 2013
Kind
B2
Abstract

The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving data to be stored, dividing data into logical data blocks, assigning the blocks to a logical block grouping comprising at least one physical data storage block from two or more of multiple solid state physical memory devices, storing the blocks in physical data storage blocks, determining a code that corresponds to the persisted data, and storing the code that corresponds to the data stored in the logical block grouping. Blocks of damaged stored data may be recovered by identifying the logical data block and logical block grouping corresponding to the damaged physical data storage block, reading the data and the code stored in the identified grouping, and comparing the code to the read data other than the data stored in the damaged block.

Claims (40)

1. A method comprising:

receiving, at a storage controller, data to be stored in solid state memory comprising multiple solid state physical memory devices;

dividing, by the storage controller, the received data into logical data blocks corresponding to the solid state memory;

assigning, by the storage controller, the logical data blocks to a logical block grouping comprising at least one physical data storage block from two or more of the multiple solid state physical memory devices;

storing the logical data blocks in physical data storage blocks, of the logical block grouping, designated for storage of persisted data within the logical block grouping;

determining, by the storage controller, a code that corresponds to the persisted data stored in the logical block grouping; and

storing, by the storage controller, the code in at least one physical data storage block designated for storage of the code that corresponds to the persisted data stored in the logical block grouping.

2. The method of claim 1 , wherein the multiple solid state physical memory devices are FLASH memory devices.

3. The method of claim 1 , wherein the determining is a logical XOR operation.

4. The method of claim 1 , wherein the multiple solid state physical memory devices and the storage controller comprise a single memory storage device, and the logical block grouping corresponds to a logical block grouping used by the storage controller to carry out memory management in the single memory storage device.

5. The method of claim 1 , wherein each of the multiple solid state physical memory devices comprises a single integrated circuit die comprising at least one physical data storage block, wherein a physical data storage block comprises a block of solid state memory formed on the integrated circuit die and is individually addressable along with other blocks of solid state memory formed on the same integrated circuit die.

6. The method of claim 1 further comprising:

recovering, by the storage controller, the persisted data stored in a selected physical data storage block by identifying the logical block grouping to which the logical data block corresponding to the selected physical data storage block is assigned, reading the persisted data and the code stored in the identified logical block grouping, and comparing the code to the read persisted data other than the persisted data stored in the selected physical data storage block.

7. The method of claim 6 , wherein the comparing is a logical XOR operation.

8. The method of claim 1 , wherein determining the code comprises:

storing, in a buffer memory, a first logical data block of the logical block grouping as a buffered value;

for each of the remaining logical data blocks in the logical block grouping,

comparing, by the storage controller, the remaining logical data block to the buffered value to determine a comparison value, and

storing the comparison value as the buffered value in the buffer memory; and

determining, by the storage controller, a value that, when compared to the buffered value, results in a predetermined value.

9. The method of claim 1 , wherein the buffer memory comprises multiple buffer memories, and at least one of the buffer memories comprises a single port memory.

10. An electronic device for storing data, comprising:

an input port configured to receive data;

a comparison buffer memory to hold a comparison value;

a comparison circuit to compare each of multiple logical blocks, into which the data is divided, to the comparison value to determine a new comparison value to hold in the comparison buffer memory; and

a solid state data storage memory to store the logical blocks and a recovery code corresponding to the comparison value, wherein data from at least one of the stored logical blocks is recoverable by combining data from one or more unselected ones of the stored logical blocks and the recovery code.

11. The device of claim 10 , wherein the solid state data storage memory is a FLASH memory.

12. The device of claim 10 , wherein the comparison circuit performs a logical XOR operation.

13. The device of claim 10 , wherein the buffer memory comprises multiple buffer memories, and at least one of the buffer memories comprises a single port memory.

14. The device of claim 10 , wherein the recovery code is determined by determining a value that, when compared to the comparison value, results in a predetermined value.

15. The device of claim 10 , comprising a processor programmed by software to effect the comparison circuit.

16. The device of claim 15 , wherein the comparison circuit performs a logical XOR operation.

17. The device of claim 10 , wherein the solid state data storage memory comprises multiple solid state physical memory devices.

18. The device of claim 17 , wherein each of the multiple solid state physical memory devices comprises a single integrated circuit die comprising at least one physical data storage block, wherein a physical data storage block comprises a block of solid state memory formed on the integrated circuit die and is individually addressable along with other blocks of solid state memory formed on the same integrated circuit die.

19. The device of claim 17 , wherein the device interfaces with a host device as a single data storage device.

20. A method comprising:

receiving a request for data stored in solid state memory comprising multiple solid state physical memory devices;

identifying, by a storage controller, a logical block grouping for logical data blocks of the requested data, the logical data blocks corresponding to the solid state memory, and the logical block grouping comprising at least one physical data storage block from two or more of the multiple solid state physical memory devices;

reading stored data and a code stored in the identified logical block grouping; and

comparing the code to the stored data to assess the requested data.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2020
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051778/0537 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2010
From: BURD, GREGORY
To: MARVELL SEMICONDUCTOR, INC.
Reel/Frame 025009/0478 →
LICENSE Recorded Sep 17, 2010
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 025009/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2010
From: MARVELL SEMICONDUCTOR, INC.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 025009/0485 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2010
From: MARVELL INTERNATIONAL, LTD.
To: MARVELL WORLD TRADE LTD.
Reel/Frame 025009/0492 →
Continuity (3)
Provisional Application 61254577 · Oct 23, 2009
Provisional Application 61242662 · Sep 15, 2009
Related Publication 20110066793A1 · Mar 17, 2011