Semiconductor device
A semiconductor device according to the present invention comprises a first transistor and a second transistor, and functions as an inverter. The first transistor includes an island semiconductor layer, a first gate insulating film surrounding the periphery of the island semiconductor layer, a gate electrode surrounding the periphery of the first gate insulating film, p+-type semiconductor layers formed in the upper and lower part of the island semiconductor layer, respectively. The second transistor includes the gate electrode, a second gate insulating film surrounding a part of the periphery of the gate electrode, an arcuate semiconductor layer contacting a part of the periphery of the second gate insulating film, n+-type semiconductor layers formed in the upper and lower part of the arcuate semiconductor layer, respectively. A first contact electrically connects the p+-type semiconductor layer in the first transistor and the n+-type semiconductor layer in the second transistor.
1. A semiconductor device comprising a first transistor and a second transistor and being allowed by the first and second transistors to function as an inverter, wherein
the first transistor includes:
an island semiconductor layer;
a first gate insulating film surrounding a periphery of the island semiconductor layer;
a gate electrode having a first surface in contact with and surrounding a periphery of the first gate insulating film;
a first-conductivity-type upper high-concentration semiconductor layer formed in an upper part of the island semiconductor layer; and
a first-conductivity-type lower high-concentration semiconductor layer formed in a lower part of the island semiconductor layer;
the second transistor includes:
the gate electrode;
a second gate insulating film in contact with and surrounding at least a part of a second surface of the gate electrode opposite from the first surface;
a semiconductor layer extending about only a portion of the gate electrode and contacting at least a part of a periphery of the second gate insulating film and separated from the gate electrode by the second gate insulating film;
a second-conductivity-type upper high-concentration semiconductor layer in an upper part of the semiconductor layer and having an opposite conductivity to the first-conductivity-type upper high-concentration semiconductor layer; and
a second-conductivity-type lower high-concentration semiconductor layer in a lower part of the semiconductor layer and having an opposite conductivity to the first-conductivity-type lower high-concentration semiconductor layer, and
the semiconductor device further comprises a first contact which electrically connects the first-conductivity-type upper high-concentration semiconductor layer in the first transistor and the second-conductivity-type upper high-concentration semiconductor layer in the second transistor together.
2. A semiconductor device comprising a first transistor and a second transistor and being allowed by the first second transistors to function as an inverter, wherein
the first transistor includes:
an island semiconductor layer;
a first gate insulating film surrounding a periphery of the island semiconductor layer;
a gate electrode having a first surface in contact with and surrounding a periphery of the first gate insulating film;
a first-conductivity-type upper high-concentration semiconductor layer in an upper part of the island semiconductor layer; and
a first-conductivity-type lower high-concentration semiconductor layer in a lower part of the island semiconductor layer;
the second transistor includes:
the gate electrode;
a second gate insulating film in contact with and surrounding at least a part of a second surface of the gate electrode opposite from the first surface;
an arc-shaped semiconductor layer extending about only a portion of the gate electrode and contacting a part of a periphery of the gate insulating film and separated from the gate electrode by the second gate insulating film;
a second-conductivity-type upper high-concentration semiconductor layer in an upper part of the arcuate semiconductor layer and having an opposite conductivity to the first-conductivity-type upper high-concentration semiconductor layer; and
a second-conductivity-type lower high-concentration semiconductor layer in a lower part of the arcuate semiconductor layer and having an opposite conductivity to the first-conductivity-type lower high-concentration semiconductor layer,
the semiconductor device further comprises a first contact which electrically connects the first-conductivity-type upper high-concentration semiconductor layer in the first transistor and the second-conductivity-type upper high-concentration semiconductor layer in the second transistor together.
3. A semiconductor device comprising a first transistor and a second transistor and being allowed by the first second transistors to function as an inverter, wherein
the first transistor includes:
an island semiconductor layer;
a first gate insulating film surrounding a periphery of the island semiconductor layer;
a gate electrode having a first surface in contact with and surrounding a periphery of the first gate insulating film;
a first-conductivity-type upper high-concentration semiconductor layer formed in an upper part of the island semiconductor layer; and
a first-conductivity-type lower high-concentration semiconductor layer formed in a lower part of the island semiconductor layer;
the second transistor includes:
the gate electrode;
a second gate insulating film in contact with and surrounding at least a part of a second surface of the gate electrode opposite from the first surface;
an arc-shaped semiconductor layer extending about only a portion of the gate electrode and contacting a part of a periphery of the second gate insulating film and separated from the gate electrode by the second gate insulating film;
a second-conductivity-type upper high-concentration semiconductor layer which is formed in an upper part of the arcuate semiconductor layer and which has an opposite conductivity to the first-conductivity-type upper high-concentration semiconductor layer; and
a second-conductivity-type lower high-concentration semiconductor layer which is formed in a lower part of the arcuate semiconductor layer and which has an opposite conductivity to the first-conductivity-type lower high-concentration semiconductor layer,
the semiconductor device further comprises:
a first semiconductor/metal compound layer formed on the first-conductivity-type upper high-concentration semiconductor layer in the first transistor;
a second semiconductor/metal compound layer formed on an extending part of the first-conductivity-type lower high-concentration semiconductor layer in the first transistor running outwardly of the first transistor and in a horizontal direction of the first transistor;
a third semiconductor/metal compound layer formed on the second-conductivity-type upper high-concentration semiconductor layer in the second transistor;
a fourth semiconductor/metal compound layer formed on an extending part of the second-conductivity-type lower high-concentration semiconductor layer in the second transistor running outwardly of the second transistor and in a horizontal direction of the second transistor;
a first contact which is formed on the first semiconductor/metal compound layer and on the third semiconductor/metal compound layer and which electrically connects the first-conductivity-type upper high-concentration semiconductor layer in the first transistor and the second-conductivity-type upper high-concentration semiconductor layer in the second transistor together; and
an output wiring electrically connected to the first contact.
4. The semiconductor device according to claim 3 , further comprising:
a second contact on the second semiconductor/metal compound layer;
a third contact on the fourth semiconductor/metal compound layer;
a fourth contact on the gate electrode;
the output wiring which is connected to the first contact and which is for outputting a signal;
an input wiring which is connected to the fourth contact and which is for inputting a signal;
a first power-source wiring connected to the second contact and to an external power source; and
a second power-source wiring connected to the third contact and to an external power source.
5. The semiconductor device according to claim 1 , wherein
the first-conductivity-type upper high-concentration semiconductor layer comprises a p+-type semiconductor layer,
the first-conductivity-type lower high-concentration semiconductor layer comprises a p+-type semiconductor layer,
the second-conductivity-type upper high-concentration semiconductor layer comprises an n+-type semiconductor layer, and
the second-conductivity-type lower high-concentration semiconductor layer comprises an n+-type semiconductor layer.
6. The semiconductor device according to claim 3 , wherein Wp≅2×Wn is satisfied where Wn is a length of an arc formed at a boundary where the arcuate semiconductor layer contacts a part of the periphery of the second gate insulating film and Wp is an outer circumference length of the island semiconductor layer.
7. The semiconductor device according to claim 3 , wherein when a length of an arc formed at a boundary where the arcuate semiconductor layer contacts a part of the periphery of the second gate insulating film is Wn and an outer circumference length of the island semiconductor layer is Wp, Wp is larger than Wn.
8. The semiconductor device according to claim 3 , wherein Ln≅Lp is satisfied where Ln is a channel length of the arcuate semiconductor layer and Lp is a channel length of the island semiconductor layer.
9. The semiconductor device according to claim 3 , wherein Wp≅2 Wn and Ln≅Lp are both satisfied where Ln is a channel length of the arcuate semiconductor layer and Lp is a channel length of the island semiconductor layer.
10. The semiconductor device according to claim 3 , wherein Wp>Wn and Ln≅Lp are both satisfied where Ln is a channel length of the arcuate semiconductor layer and Lp is a channel length of the island semiconductor layer.
11. The semiconductor device according to claim 1 , wherein
the first transistor comprises an enhancement-type nMOS transistor,
the first-conductivity-type upper high-concentration semiconductor layer comprises a p+-type semiconductor layer,
the first-conductivity-type lower high-concentration semiconductor layer comprises a p+-type semiconductor layer,
the second transistor is an enhancement-type pMOS transistor,
the second-conductivity-type upper high-concentration semiconductor layer comprises an n+-type semiconductor layer, and
the second-conductivity-type lower high-concentration semiconductor layer comprises an n+-type semiconductor layer, and
the gate electrode comprises a material that causes the nMOS transistor and the pMOS transistor to be an enhancement-type transistor.
12. The semiconductor device according to claim 3 , wherein all of the first to fourth semiconductor/metal compound layers comprise a compound layer of silicon and metal.
13. The semiconductor device according to claim 2 , wherein
the first and second transistors are an enhancement-type nMOS transistor and an enhancement-type pMOS transistor, respectively,
the island semiconductor layer comprises an island silicon layer,
the arcuate semiconductor layer comprises an arcuate silicon layer,
both of the first-conductivity-type upper high-concentration semiconductor layer and the first-conductivity-type lower high-concentration semiconductor layer comprise a p+-type silicon layer, and
both of the second-conductivity-type upper high-concentration semiconductor layer and the second-conductivity-type lower high-concentration semiconductor layer comprises an n+-type silicon layer.
14. The semiconductor device according to claim 13 , wherein
the island silicon layer comprises an n-type or none-doped island silicon layer, and
the arcuate silicon layer comprises a p-type or none-doped arcuate silicon layer.