Multiple gigahertz clock-data alignment scheme
View Patent ↗A transmitting system includes a clock system and a data system. The clock system is configured to receive a clock having a first value and produce a control signal having a second, different value and an output clock having the first value. The data system is configured to receive data and the control signal and to align the data with the output clock, based on the control signal, to produce output data. The clock system includes a driver configured to produce the output clock, a divider configured to divide the received clock, and a phase interpolator configured to rotate the divided clock to produce the control signal. Also, the data is parallel data, and the data system includes a multiplexer configured to receive the parallel data and to use the control signal to serialize the parallel data as the aligned data and a driver configured to produce the output data.
1. A transmitting system comprising:
a clock system configured to:
receive a clock having a value,
produce a first control signal and a second control signal, and
generate an output clock having the received clock value; and
a data system configured to:
receive data at a first data channel and a second data channel;
receive the first and second control signals, wherein the first and second control signals are configured to independently control respective ones of the first and second data channels;
align the data in the first and second data channels with the output clock based on respective ones of the first and second control signals; and
produce output data.
2. The transmitting system of claim 1 , wherein the clock system comprises:
a driver configured to produce the output clock;
a divider configured to divide the received clock; and
a first phase interpolator and a second phase interpolator configured to rotate a divided clock to produce respective ones of the first and second control signals.
3. The transmitting system of claim 2 , wherein the divider comprises a denominator of 2 to produce a half speed clock.
4. The transmitting system of claim 1 , wherein the data comprises parallel data, and the data system comprises:
a multiplexer configured to receive the parallel data and to serialize the parallel data as the aligned data; and
a driver configured to produce the output data.
5. The transmitting system of claim 4 , wherein the multiplexer is configured to temporally adjust the parallel data to produce the aligned data, such that a range of adjustment of the parallel data to produce the aligned data is approximately greater or smaller than 1 clock period.
6. The transmitting system of claim 1 , wherein the clock system comprises:
a driver configured to produce the output clock;
a divider configured to divide the received clock in half and to produce first and second half clocks; and
first and second rotators configured to rotate respective ones of the first and second half clocks to produce respective ones of the first and second control signals.
7. The transmitting system of claim 1 , wherein the data system comprises:
a first aligning system in the first data channel; and
a second aligning system in the second data channel.
8. The transmitting system of claim 7 , wherein:
the first aligning system comprises:
first and second multiplexers configured to receive the first control signal;
first and second preemphasis amplifiers coupled to outputs of respective ones of the first and second multiplexers;
a first summer configured to sum outputs from the first and second preemphasis amplifiers; and
a first driver coupled to an output of the first summer and configured to produce a first output data; and
the second aligning system comprises:
third and fourth multiplexers configured to receive the second control signal;
third and fourth preemphasis amplifiers coupled to outputs of respective ones of the third and fourth multiplexers;
a second summer configured to sum outputs from the third and fourth preemphasis amplifiers; and
a second driver coupled to an output of the second summer and configured to produce a second output data.
9. The transmitting system of claim 8 , further comprising:
a first retiming device located before the second multiplexer in the first aligning system; and
a second retiming device located before the fourth multiplexer in the second aligning system.
10. The transmitting system of claim 1 , wherein the transmitting system is included within a serializer of a serializer-deserializer (SERDES) apparatus.
11. A system, comprising:
a deserializer configured to receive serial data and produce parallel data and a clock; and
a serializer configured to receive the parallel data and the clock and to produce serial output data and an output clock, the serializer comprising a transmitter, the transmitter comprising:
a clock system configured to:
receive the clock having a value,
produce a first control signal and a second control signal, and
generate the output clock having the received clock value; and
a data system configured to;
receive the parallel data at a first data channel and a second data channel;
receive the first and second control signals, wherein the first and second control signals are configured to independently control respective ones of the first and second data channels;
align the parallel data in the first and second data channels with the output clock based on respective ones of the first and second control signals; and
produce the serial output data.
12. The system of claim 11 , wherein the clock system comprises:
a driver configured to produce the output clock;
a divider configured to divide the input clock in half; and
a first phase interpolator and a second phase interpolator configured to rotate a divided clock to produce respective ones of the first and second control signals.
13. The system of claim 11 , wherein the data system comprises:
a multiplexer configured to receive the parallel data and to serialize the parallel data as the aligned data; and
a driver configured to produce the output data.
14. The system of claim 11 , wherein the clock system comprises:
a driver configured to produce the output clock;
a divider configured to divide the input clock in half and to produce first and second half clocks; and
first and second rotators configured to rotate respective ones of the first and second half clocks to produce respective ones of the first and second control signals.
15. The system of claim 11 , wherein the data system comprises:
a first aligning system comprising:
first and second multiplexers configured to receive the first control signal;
first and second preemphasis amplifiers coupled to outputs of respective ones of the first and second multiplexers;
a first summer configured to sum outputs from the first and second preemphasis amplifiers; and
a first driver coupled to an output of the first summer and configured to produce a first output data; and
a second aligning system comprising:
third and fourth multiplexers configured to receive the second control signal;
third and fourth preemphasis amplifiers coupled to outputs of respective ones of the third and fourth multiplexers;
a second summer configured to sum outputs from the third and fourth preemphasis amplifiers; and
a second driver coupled to an output of the second summer and configured to produce a second output data.
16. The system of claim 15 , further comprising:
a first retiming device located before the second multiplexer in the first aligning system; and
a second retiming device located before the fourth multiplexer in the second aligning system.