Flat panel display and method for fabricating the same
View Patent ↗A flat panel display, having an anti-electrostatic configuration, comprising a plurality of gate lines and data lines formed on an insulating substrate having an emission region and a pad portion, an anti-electrostatic wire initially coupling the gate lines, and an anti-electrostatic circuit coupled to a data line. The anti-electrostatic wire between a gate line and an adjacent gate line is subsequently cut by an opening for cutting the anti-electrostatic wire to electrically isolate the respective gate lines.
1. A method for fabricating a flat panel display, comprising:
forming a gate electrode and an anti-electrostatic wire on a first insulating layer;
forming a second insulating layer having an opening exposing a portion of the anti-electrostatic wire;
forming a conductive layer;
patterning the conductive layer to form a source electrode and a drain electrode while removing the portion of the anti-electrostatic wire exposed by the opening; and
forming a passivation layer on the source electrode and the drain electrode,
wherein the passivation layer contacts the source electrode, the drain electrode, and the first insulating layer.
2. The method of claim 1 , wherein the gate electrode and the anti-electrostatic wire are made of a double conductive layer.
3. The method of claim 2 , wherein the double conductive layer comprises an MoW layer and an AlNd layer.
4. The method of claim 3 ,
where the Mow layer is formed on the AlNd layer; and
wherein the MoW layer is removed while forming the opening.
5. The method of claim 1 , wherein the opening is wider than the anti-electrostatic wire.
6. The method of claim 5 , wherein when patterning the conductive layer, all of the anti-electrostatic wire exposed by the opening is removed.
7. The method of claim 1 , further comprising forming the conductive layer on the second insulating layer.
8. The method claim 7 , further comprising:
forming an active layer in an emission region of a substrate having the emission region and a pad portion;
forming source and drain regions in the active layer; and
forming a first contact hole and a second contact hole in the second insulating layer exposing a portion of the source region and the drain region, respectively.