Frequency synchronization using clock recovery loop with adaptive packet filtering
An endpoint or other communication device of a communication system includes a clock recovery loop having a phase error estimator. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery loop is configured to control a slave clock of the slave device responsive to a phase error estimate generated by the phase error estimator so as to synchronize the slave clock with a master clock of the master device. The phase error estimator comprises a plurality of filters each configured to generate a different estimate of master clock phase using at least a subset of a plurality of packets received from the master device, and control logic for adaptively selecting at least a particular one of the plurality of filters for use in generating the phase error estimate to be processed in the clock recovery loop.
1. An apparatus comprising:
a communication device comprising a clock recovery loop having a phase error estimator;
the communication device being operative as a slave device relative to another communication device that is operative as a master device;
the clock recovery loop being configured to control a slave clock of the slave device responsive to a phase error estimate generated by the phase error estimator so as to synchronize the slave clock with a master clock of the master device;
the phase error estimator comprising a plurality of filters each configured to generate a different estimate of master clock phase using at least a subset of a plurality of packets received from the master device, and control logic for adaptively selecting at least a particular one of the plurality of filters for use in generating the phase error estimate to be processed in the clock recovery loop.
2. The apparatus of claim 1 wherein a given one of the master clock phase estimates is determined based on measured master-to-slave delays associated with respective ones of the received packets in the corresponding subset.
3. The apparatus of claim 2 wherein the measured master-to-slave delay associated with a particular one of the received packets is computed based on a difference between an arrival timestamp generated in the slave device and a corresponding departure timestamp generated in the master device, wherein the departure timestamp is communicated from the master device to the slave device in the particular received packet.
4. The apparatus of claim 1 wherein a given one of the master clock phase estimates is determined based on measured slave-to-master delays associated with respective ones of the received packets in the corresponding subset.
5. The apparatus of claim 4 wherein the measured slave-to-master delay associated with a particular one of the received packets is computed based on a difference between a departure timestamp generated in the slave device and a corresponding arrival timestamp generated in the master device, wherein the arrival timestamp is communicated from the master device to the slave device in the particular received packet.
6. The apparatus of claim 1 wherein one of the plurality of filters generates an estimate of the master clock phase utilizing a predetermined function of measured delays of multiple ones of a plurality of packets received within a specified window.
7. The apparatus of claim 6 wherein one of the plurality of filters generates an estimate of the master clock phase utilizing selected packets each of which exhibits a minimum measured delay of the plurality of packets received within the specified window.
8. The apparatus of claim 6 wherein one of the plurality of filters generates an estimate of the master clock phase utilizing selected packets each of which exhibits a maximum measured delay of the plurality of packets received within the specified window.
9. The apparatus of claim 6 wherein one of the plurality of filters generates an estimate of the master clock phase utilizing a mean of measured delays of multiple ones of the plurality of packets received within the specified window.
10. The apparatus of claim 6 wherein the plurality of filters comprises:
a sample-minimum filter configured to generate an estimate of the master clock phase utilizing selected packets each of which exhibits a minimum measured delay of the plurality of packets received within the specified window;
a sample-maximum filter configured to generate an estimate of the master clock phase utilizing selected packets each of which exhibits a maximum measured delay of the plurality of packets received within the specified window; and
a sample-mean filter configured to generate an estimate of the master clock phase utilizing a mean of measured delays of multiple ones of the plurality of packets received within the specified window.
11. The apparatus of claim 1 wherein the control logic comprises a variance estimator configured to generate variance measures for respective ones of the master clock phase estimates, and wherein the control logic adaptively selects at least a particular one of the plurality of filters based on the variance measures.
12. The apparatus of claim 1 wherein the control logic comprises a state machine having states corresponding to respective ones of the filters with the adaptive selection of the particular one of the filters being based upon the current state of the state machine and wherein movement from state to state in the state machine is based on characteristics of the corresponding master clock phase estimates.
13. The apparatus of claim 12 wherein the characteristics of the master clock phase estimates comprise phase error variances.
14. The apparatus of claim 1 wherein the control logic adaptively selects a particular one of the plurality of filters for use in generating the phase error estimate to be provided to the clock recovery loop based on which of the master clock phase estimates has the lowest associated phase noise.
15. The apparatus of claim 1 wherein the phase error estimate is based on a combination of two or more of the master clock phase error estimates.
16. The apparatus of claim 15 wherein in generating the phase error estimate said two or more of the master clock phase error estimates are combined in a weighted manner based on their respective variances.
17. The apparatus of claim 1 wherein the phase error estimate is based on a combination of at least one master clock phase estimate provided by said selected at least one filter and an additional master clock phase estimate generated for packet flow in a direction from the slave device to the master device.
18. The apparatus of claim 1 wherein the communication device comprises a processor coupled to a memory, and the clock recovery loop is implemented at least in part in software code that is stored in the memory and executed by the processor.
19. The apparatus of claim 1 wherein the apparatus is implemented at least in part in the form of an integrated circuit.
20. A method for use in a communication device, the communication device being operative as a slave device relative to another communication device that is operative as a master device, the method comprising the steps of:
receiving packets from the master device;
generating an estimate of phase error between a master clock of the master device and a slave clock of the slave device; and
controlling the slave clock based on the phase error estimate to synchronize the slave clock with the master clock;
wherein the generating step comprises generating a plurality of different estimates of master clock phase with each such master clock phase estimate being based on at least a subset of the packets received from the master device, and adaptively selecting at least a particular one of the master clock phase estimates for use in generating the phase error estimate.
21. A computer program product comprising a processor-readable storage medium having embodied therein executable program code that when executed by a processor of the communication device implements the steps of the method of claim 20 .
22. A communication system, comprising:
at least first and second communication devices configured to communicate with one another over a packet network;
a first one of the communication devices being operative as a slave device relative to another one of the communication devices operative as a master device;
the first communication device comprising a clock recovery loop having a phase error estimator;
the clock recovery loop being configured to control a slave clock of the slave device responsive to a phase error estimate generated by the phase error estimator so as to synchronize the slave clock with a master clock of the master device;
the phase error estimator comprising a plurality of filters each configured to generate a different estimate of master clock phase using at least a subset of a plurality of packets received from the master device, and control logic for adaptively selecting at least a particular one of the plurality of filters for use in generating the phase error estimate to be processed in the clock recovery loop.
23. The apparatus of claim 1 wherein the phase error estimator is configured to generate the phase error estimate based at least in part on one or more arrival and departure timestamps associated with respective ones of the received packets.