IP Library › Granted Patent US 8,264,045
Granted Patent B2
US 8,264,045 · App. 12/886,036 · Granted Sep 11, 2012

Semiconductor device including a SRAM section and a logic circuit section

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Quick Facts
Patent No.
US 8,264,045
App. No.
12/886,036
Granted
Sep 11, 2012
Kind
B2
Abstract

A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.

Claims (38)

1. A semiconductor device including a SRAM section and a logic circuit section, comprising:

a first p-type MIS transistor including a first p-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and

a second p-type MIS transistor including a second p-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section,

wherein a first impurity concentration of a first p-type impurity in the first p-type gate electrode is lower than a second impurity concentration of a second p-type impurity in the second p-type gate electrode.

2. The semiconductor device of claim 1 , further comprising:

a first n-type MIS transistor including a first n-type gate electrode formed with a third gate insulating film interposed on a third element formation region of the semiconductor substrate in the SRAM section; and

a first element isolation region formed between the first element formation region and the third element formation region of the semiconductor substrate,

wherein the first p-type gate electrode is integrally formed with the first n-type gate electrode.

3. The semiconductor device of claim 2 ,

wherein a third impurity concentration of a n-type impurity in the first n-type gate electrode is higher than the first impurity concentration.

4. The semiconductor device of claim 2 ,

wherein a pn boundary between the first p-type gate electrode and the first n-type gate electrode is located at a point on the first element isolation region.

5. The semiconductor device of claim 2 , further comprising:

a second n-type MIS transistor including a second n-type gate electrode formed with a fourth gate insulting film interposed on a fourth element formation region of the semiconductor substrate in the logic circuit section; and

a second element isolation region formed between the second element formation region and the fourth element formation region of the semiconductor substrate,

wherein the second p-type gate electrode is formed integrally with the second n-type gate electrode.

6. The semiconductor device of claim 5 ,

wherein a pn boundary between the second p-type gate electrode and the second n-type gate electrode is located at a point on the second element isolation region.

7. The semiconductor device of claim 5 ,

wherein the first element isolation region has a width in a gate width direction smaller than the second element isolation region.

8. The semiconductor device of claim 7 ,

wherein a first pn boundary between the first p-type gate electrode and the first n-type gate electrode is located at a point on the first element isolation region,

a second pn boundary between the second p-type gate electrode and the second n-type gate electrode is located at a point on the second element isolation region, and

a distance from a center of the first element isolation region in the gate width direction to the first pn boundary is smaller than a distance from a center of the second element isolation region in the gate width direction to the second pn boundary.

9. The semiconductor device of claim 5 ,

wherein a first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.

10. The semiconductor device of claim 5 ,

wherein the first n-type gate electrode has a width in a gate width direction smaller than the second n-type gate electrode.

11. The semiconductor device of claim 5 ,

wherein the third gate insulating film and the fourth gate insulating film are formed of a same insulting film.

12. The semiconductor device of claim 5 ,

wherein the first n-type gate electrode and the second n-type gate electrode are polysilicon electrodes.

13. The semiconductor device of claim 1 ,

wherein the first p-type gate electrode has a width in a gate width direction smaller than the second p-type gate electrode.

14. The semiconductor device of claim 1 ,

wherein the first gate insulating film and the second gate insulating film are formed of a same insulting film.

15. The semiconductor device of claim 1 ,

wherein the first p-type gate electrode and the second p-type gate electrode are polysilicon electrodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2014
From: PANASONIC CORPORATION (FORMERLY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.)
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 032152/0514 →