Microcode configurable frequency clock
View Patent ↗A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the desired speed of comparison. The logic circuit is configured to receive an input clock signal and to produce an output clock signal by frequency dividing the input signal based on the microcode generated data. The output clock is used to control the speed of comparison in the optical transceiver.
1. A microcode configurable frequency clock for controlling a comparator comprising:
a memory configured to receive microcode generated data that controls a speed of comparison for the comparator; and
a logic circuit that is configured to receive an input clock signal and frequency process the input clock signal as directed by the microcode generated data to generate an output clock signal that is adapted to control the speed of comparison for the comparator.
2. The microcode configurable frequency clock for controlling a comparator in accordance with claim 1 , wherein the memory is one of a register, a flip-flop, Random Access Memory (RAM), or a non-volatile memory.
3. The microcode configurable frequency clock for controlling a comparator in accordance with claim 1 , wherein the memory receives the microcode generated data from a microprocessor.
4. The microcode configurable frequency clock for controlling a comparator in accordance with claim 1 , wherein the logic circuit is a counter.
5. The microcode configurable frequency clock for controlling a comparator in accordance with claim 1 , wherein the logic circuit includes a matching circuit.
6. The microcode configurable frequency clock for controlling a comparator in accordance with claim 1 , wherein the logic circuit includes an edge detector.
7. The microcode configurable frequency clock for controlling a comparator in accordance with claim 1 , wherein the logic circuit includes a transition clock circuit.
8. The microcode configurable frequency clock for controlling a comparator in accordance with claim 1 , wherein the logic circuit includes an incrementor.
9. The microcode configurable frequency clock for controlling a comparator in accordance with claim 1 , wherein the microcode configurable frequency clock is implemented in an optical transceiver.
10. A system comprising:
a comparator comprising a digital to analog converter (DAC); and
a microcode configurable frequency clock for controlling a speed of comparison for the comparator, the microcode configurable frequency clock comprising:
a memory configured to receive microcode generated data that controls the speed of comparison for the comparator; and
a logic circuit that is configured to receive an input clock signal and frequency process the input clock signal as directed by the microcode generated data to generate an output clock signal that is adapted to control the speed of comparison for the comparator.
11. The system of claim 10 , wherein the memory is one of a register, a flip-flop, Random Access Memory (RAM), or a non-volatile memory.
12. The system of claim 10 , wherein the memory is configured to receive the microcode generated data from a microprocessor.
13. The system of claim 10 , wherein the logic circuit is a counter.
14. The system of claim 10 , wherein the logic circuit comprises:
a register;
a matching circuit coupled to the memory and to the register;
a transition clock circuit coupled to an output of the matching circuit;
a reset circuit coupled between the output of the matching circuit and an input of the register;
an incrementor coupled to the register; and
an edge detector coupled to the incrementor.
15. The system of claim 10 , wherein the microcode configurable frequency clock is implemented in an optical transceiver.
16. A microcode configurable frequency clock for controlling a comparator, the microcode configurable frequency clock comprising:
a memory configured to receive microcode generated data that controls a speed of comparison for the comparator, wherein the microcode generated data includes a first set of bits that define high pulse widths and a second set of bits independent from the first set of bits that define low pulse widths of an output clock signal; and
a logic circuit that is configured to:
receive an input clock signal comprising a high pulse and a low pulse;
frequency process the input clock signal high pulse as directed by the microcode generated data to generate a high pulse of the output clock signal; and
frequency process the input clock signal low pulse as directed by the microcode generated data to generate a low pulse of the output clock signal, wherein the high pulse and the low pulse of the output clock signal control the speed of comparison for the comparator.
17. The microcode configurable frequency clock of claim 16 , wherein a speed of the high pulse of the output clock signal is greater than a speed of the low pulse of the output clock signal.
18. The microcode configurable frequency clock of claim 16 , wherein a speed of the low pulse of the output clock signal is greater than a speed of the high pulse of the output clock signal.
19. The microcode configurable frequency clock of claim 16 , wherein the memory comprises at least one of a register, a flip-flop, Random Access Memory (RAM), or a non-volatile memory.
20. The microcode configurable frequency clock of claim 16 , wherein the microcode configurable frequency clock is implemented in an optical transceiver.