Electronic device for power-on-reset
View Patent ↗An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a first power supply voltage level exceeds a threshold voltage level and a first inverter and a second inverter being cross-coupled. An output of the second inverter is the POR output of the power-up reset circuit. The output is coupled to the trigger stage for switching the trigger stage off in response to a change of a signal at the output of the second inverter. The first inverter is dimensioned to follow with a voltage level at an output an initially rising slope of the first power supply voltage level and the second inverter is dimensioned to keep a voltage level at an output at a second power supply voltage level during the initially rising slope of the first power supply voltage level.
1. An apparatus comprising:
a voltage rail;
a trigger stage having:
a PMOS transistor that is coupled to the voltage rail at its source;
a voltage divider that is coupled drain of the PMOS transistor;
a first NMOS transistor that is coupled to the voltage divider at its gate;
a first resistor that is coupled between the voltage rail and the first NMOS transistor at its drain;
a first inverter that is coupled to the drain of the first NMOS transistor; and
a second NMOS transistor that is coupled to the first inverter at its gate;
a second inverter that is coupled to the gate of the PMOS transistor and the drain of the second NMOS transistor, wherein the second inverter includes a switch that is coupled to the first inverter;
a third inverter that is coupled to the gate of the PMOS transistor and the drain of the second NMOS transistor; and
an output buffer that is coupled to the third inverter.
2. The apparatus of claim 1 , wherein the PMOS transistor is a first PMOS transistor, and wherein the switch further comprises a second PMOS transistor.
3. The apparatus of claim 2 , wherein the second inverter further comprises:
a third PMOS transistor that is coupled to the source of the second PMOS transistor at its drain, the gate of the first PMOS transistor at its gate, and the voltage rail at its source; and
a third NMOS transistor that is coupled to the drain of the second NMOS transistor and the drain of the second PMOS transistor at its drain and the gate of the first PMOS transistor at its gate.
4. The apparatus of claim 3 , wherein the output buffer further comprises a plurality of output inverters coupled in series with one another.
5. The apparatus of claim 4 , wherein the third inverter further comprises:
a fourth PMOS transistor that is coupled to the drain of the second NMOS transistor at its gate, the gate of the first PMOS transistor at its drain, and the voltage rail at its source; and
a fourth NMOS transistor that is coupled to the gate of the first PMOS transistor at its drain and the drain of the second NMOS transistor at its gate.
6. An apparatus comprising:
a voltage rail;
a trigger stage having:
a first PMOS transistor that is coupled to the voltage rail at its source;
a voltage divider that is coupled drain of the first PMOS transistor;
a first NMOS transistor that is coupled to the voltage divider at its gate;
a first resistor that is coupled between the voltage rail and the first NMOS transistor at its drain;
a first inverter that is coupled to the drain of the first NMOS transistor; and
a second NMOS transistor that is coupled to the first inverter at its gate;
a second inverter having:
a second PMOS transistor that is coupled to the first inverter at its gate;
a third PMOS transistor that is coupled to the source of the second PMOS transistor at its drain, the gate of the first PMOS transistor at its gate, and the voltage rail at its source; and
a third NMOS transistor that is coupled to the drain of the second NMOS transistor and the drain of the second PMOS transistor at its drain and the gate of the first PMOS transistor at its gate, wherein the aspect ratios of each of the second and third PMOS transistors is greater than the aspect ratio of the third NMOS transistor;
a third inverter that is coupled to the gate of the PMOS transistor and the drain of the second NMOS transistor; and
an output buffer that is coupled to the third inverter.
7. The apparatus of claim 6 , wherein the output buffer further comprises a plurality of output inverters coupled in series with one another.
8. The apparatus of claim 7 , wherein the third inverter further comprises:
a fourth PMOS transistor that is coupled to the drain of the second NMOS transistor at its gate, the gate of the first PMOS transistor at its drain, and the voltage rail at its source; and
a fourth NMOS transistor that is coupled to the gate of the first PMOS transistor at its drain and the drain of the second NMOS transistor at its gate.