IP Library Patent Application 12887836
Patent Application
App. No. 12/887,836

DISPLAY PANEL

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Quick Facts
Patent No.
US None
App. No.
12/887,836
Abstract

A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line.

Claims (55)

1 . A display panel comprising:

an insulation substrate including a display area and a peripheral area;

wires disposed on the insulation substrate in the display area;

a first testing line and a second testing line disposed on the insulation substrate and aligned substantially parallel to each other; and

a diode unit disposed between the wires and one of the first testing line and the second testing line,

wherein the wires extend from the display area into the peripheral area and through diodes included in the diode unit, and

the wires are electrically connected to the one of the first testing line and the second testing line.

2 . The display panel of claim 1 , wherein

an input terminal and an output terminal of each of the diodes are formed with different wiring layers on the insulation substrate.

3 . The display panel of claim 1 , wherein each of the diodes is a diode connected thin film transistor.

4 . The display panel of claim 3 , wherein the thin film transistor comprises:

a gate electrode formed with a same layer as a gate line on the insulation substrate;

a source electrode formed with a same layer as a data line on the insulation substrate; and

and a drain electrode formed with the same layer as the data line on the insulation substrate.

5 . The display panel of claim 4 , wherein

a gate insulating layer and a semiconductor layer are disposed between the gate electrode and the drain electrode of the thin film transistor.

6 . The display panel of claim 5 , wherein

a portion of the semiconductor layer is disposed under the drain electrode to have a same boundary as a boundary of the drain electrode on the insulation substrate.

7 . The display panel of claim 5 , wherein

an ohmic contact layer is disposed between the semiconductor layer and the drain electrode.

8 . The display panel of claim 1 , wherein

a cutting line is disposed between the one of the first testing line and the second testing line and the diode unit to electrically disconnect the one of the first testing line and the second testing line from the diodes of the diode unit.

9 . The display panel of claim 8 , wherein

a distance between the cutting line and the diodes is about 200 micrometers.

10 . The display panel of claim 1 , further comprising

a shorting bar disposed substantially parallel to the one of the first testing line and the second testing line on the insulating substrate, wherein the shorting bar connects two or more of the wires to each other.

11 . The display panel of claim 1 , further comprising

a static electricity protection circuit disposed on the insulating substrate between the diode unit and the wires to dissipate static electricity between the wires and the diode unit.

12 . The display panel of claim 1 , further comprising

a pad disposed on the insulating substrate between the wires and the diode unit, wherein the pad supplies a signal to the wires from an external source.

13 . The display panel of claim 1 , further comprising

a pad disposed on a side of the insulating substrate opposite to a side thereof on which the diode unit is disposed, wherein the pad supplies a signal to the wires from an external source.

14 . The display panel of claim 1 , wherein

the wires comprise one of data and or gate lines.

15 . A display panel comprising:

an insulation substrate including a display area and a peripheral area;

wires disposed in the display area; and

a diode unit connected to portions of the wires which extend into the peripheral area from the display area,

wherein the wires pass through diodes in the diode unit and extend such that one end of the wires corresponds to an edge of the insulation substrate.

16 . The display panel of claim 15 , wherein

an input terminal and an output terminal of each of the diodes are formed with different wiring layers on the insulation substrate.

17 . The display panel of claim 15 , wherein

each of the diodes is a diode connected thin film transistor,

the thin film transistor comprises:

a gate electrode formed with a same layer as the gate line;

a source electrode formed with a same layer as a data line; and

a drain electrode formed with the same layer as the data line, and

a gate insulating layer and a semiconductor layer are disposed between the gate electrode and the drain electrode of the thin film transistor.

18 . The display panel of claim 17 , wherein

a portion of the semiconductor layer is disposed under the drain electrode to have a same boundary as a boundary of the drain electrode on the insulation substrate.

19 . The display panel of claim 15 , wherein

a distance from a cutting line to the diodes is about 200 micrometers.

20 . The display panel of claim 15 , further comprising

a pad which supplies a signal to the wires from an external source,

wherein the pad is disposed one of between the diode unit and the wires and at a side of the insulating substrate opposite to a side thereof on which the diode unit is disposed.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029151/0055 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2010
From: KOO, BON-YONG; KIM, KYUNG-WOOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025028/0975 →