IP Library Granted Patent US 8,541,257
Granted Patent B2
US 8,541,257 · App. 12/888,180 · Granted Sep 24, 2013

Aligned polymers for an organic TFT

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Quick Facts
Patent No.
US 8,541,257
App. No.
12/888,180
Granted
Sep 24, 2013
Kind
B2
Abstract

A method for forming an electronic device having a semiconducting active layer comprising a polymer, the method comprising aligning the chains of the polymer parallel to each other by bringing the polymer into a liquid-crystalline phase.

Claims (11)

1. A method for forming a transistor comprising the step of forming an active interface of the transistor between a semiconductive layer and a gate insulator layer by solution deposition of a second polymer layer on top of a solution-processed polymer layer that has not been converted into an insoluble form prior to the deposition of the second polymer layer.

2. A method as claimed in claim 1 wherein the second layer forms the gate insulator of the transistor.

3. A method as claimed in claim 1 , wherein the second layer comprises PVP.

4. A method as claimed in claim 1 , wherein the said semiconductive layer is the said solution-processed polymer layer.

5. A method as claimed in claim 1 , wherein the said solution-processed polymer layer is soluble in a non-polar organic solvent, but is insoluble in a polar solvent.

6. A method as claimed in claim 5 , wherein the second polymer layer is deposited from a polar organic solvent, in which the said solution-processed polymer layer is not soluble.

7. A method as claimed in claim 1 , wherein the second polymer layer is deposited from an alcohol, a protic polar solvent such as water or an aprotic polar solvent such as DMF.

8. A method as claimed in claim 1 , wherein a source-drain and/or gate electrode of the transistor is also formed from solution.

9. A method according to claim 1 , wherein the second layer is the gate insulator layer, and the solution-processed polymer layer is a uniaxially aligned liquid crystal polymer film.

10. A method for forming a transistor comprising the step of forming an active interface of the transistor between a semiconductive layer and a gate insulator layer by solution deposition of a second polymer layer on top of a solution-processed polymer layer that has not been converted into an insoluble form prior to the deposition of the second polymer layer,

wherein the forming comprises omission of an alignment layer to induce polymer chain alignment in the semiconductive layer.

Assignments (2)
CHANGE OF NAME Recorded May 5, 2016
From: PLASTIC LOGIC LIMITED
To: FLEXENABLE LIMITED
Reel/Frame 038617/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2013
From: CAMBRIDGE ENTERPRISE LIMITED
To: PLASTIC LOGIC LIMITED
Reel/Frame 030484/0180 →