Reference voltage circuit
View Patent ↗Provided is a reference voltage circuit in which a temperature characteristic of a reference voltage is excellent and a circuit scale is small. In the reference voltage circuit, for example, a temperature correction circuit separated from the reference voltage circuit is not used and a difference voltage between threshold voltages of two E-type NMOS transistors ( 14 and 15 ) is added to a threshold voltage of a D-type NMOS transistor to generate a reference voltage (Vref). Therefore, the influence of the D-type NMOS transistor on the reference voltage (Vref), which is a degradation factor of the temperature characteristic of the reference voltage (Vref), may be reduced to suppress a change in tilt and curve of the reference voltage (Vref) with respect to a temperature.
1. A reference voltage circuit, comprising:
a first depletion type NMOS transistor including:
a gate connected to a first terminal; and
a drain connected to a power supply terminal;
a second depletion type NMOS transistor including:
a gate connected to the gate of the first depletion type NMOS transistor;
a source connected to a second terminal; and
a drain connected to the power supply terminal;
a first NMOS transistor including:
a drain connected to the first terminal; and
a source connected to a ground terminal;
a second NMOS transistor including:
a gate connected to a drain thereof, a gate of the first NMOS transistor, and the second terminal; and
a source connected to a reference voltage output terminal,
the second NMOS transistor having a threshold voltage lower than a threshold voltage of the first NMOS transistor; and
a voltage generation circuit including a third depletion type NMOS transistor, for generating a reference voltage between the reference voltage output terminal and the ground terminal.
2. A reference voltage circuit according to claim 1 , wherein:
the first depletion type NMOS transistor further includes a source connected to the gate thereof; and
the third depletion type NMOS transistor included in the voltage generation circuit includes:
a gate connected to the ground terminal;
a source connected to the ground terminal; and
a drain connected to the reference voltage output terminal.
3. A reference voltage circuit according to claim 1 , wherein:
the first depletion type NMOS transistor further includes a source connected to the gate thereof;
the voltage generation circuit further comprises:
a third enhancement type NMOS transistor including:
a source connected to the ground terminal; and
a drain connected to the reference voltage output terminal; and
a fourth enhancement type NMOS transistor including:
a gate connected to a drain thereof and a gate of the third enhancement type NMOS transistor; and
a source connected to the ground terminal; and
the third depletion type NMOS transistor includes:
a gate connected to a source thereof and the drain of the fourth enhancement type NMOS transistor; and
a drain connected to the power supply terminal.
4. A reference voltage circuit according to claim 1 , wherein:
the first depletion type NMOS transistor further includes a source connected to the gate thereof;
the voltage generation circuit further comprises:
a third enhancement type NMOS transistor including:
a source connected to the ground terminal; and
a drain connected to the reference voltage output terminal; and
a fourth enhancement type NMOS transistor including:
a gate connected to a drain thereof and a gate of the third enhancement type NMOS transistor; and
a source connected to the ground terminal; and
the third depletion type NMOS transistor includes:
a gate connected to the gate of the first depletion type NMOS transistor;
a source connected to the drain of the fourth enhancement type NMOS transistor; and
a drain connected to the power supply terminal.
5. A reference voltage circuit according to claim 1 , wherein:
the voltage generation circuit further comprises:
a third enhancement type NMOS transistor including:
a source connected to the ground terminal; and
a drain connected to the reference voltage output terminal; and
a fourth enhancement type NMOS transistor including:
a gate connected to a drain thereof and a gate of the third enhancement type NMOS transistor; and
a source connected to the ground terminal; and
the third depletion type NMOS transistor includes:
a gate connected to a source thereof, the gate of the first depletion type NMOS transistor, and the drain of the fourth enhancement type NMOS transistor; and
a drain connected to the power supply terminal.
6. A reference voltage circuit according to claim 1 , wherein each of the first NMOS transistor and the second NMOS transistor is of an enhancement type.
7. A reference voltage circuit according to claim 1 , wherein:
the first NMOS transistor is of an enhancement type; and
the second NMOS transistor is of a depletion type.
8. A reference voltage circuit, comprising:
a first enhancement type PMOS transistor including:
a source connected to a power supply terminal; and
a drain connected to a first terminal;
a second enhancement type PMOS transistor including:
a gate connected to a drain thereof, a gate of the first enhancement type PMOS transistor, and a second terminal; and
a source connected to the power supply terminal;
a first NMOS transistor including:
a gate connected to a drain thereof and the first terminal; and
a source connected to a ground terminal;
a second NMOS transistor including:
a gate connected to the gate of the first NMOS transistor;
a drain connected to the second terminal; and
a source connected to a reference voltage output terminal,
the second NMOS transistor having a threshold voltage lower than a threshold voltage of the first NMOS transistor; and
a voltage generation circuit including a third depletion type NMOS transistor, for generating a reference voltage between the reference voltage output terminal and the ground terminal.
9. A reference voltage circuit according to claim 8 , wherein the third depletion type NMOS transistor included in the voltage generation circuit includes:
a gate connected to the ground terminal;
a source connected to the ground terminal; and
a drain connected to the reference voltage output terminal.
10. A reference voltage circuit according to claim 8 , wherein:
the voltage generation circuit further comprises:
a third enhancement type NMOS transistor including:
a source connected to the ground terminal; and
a drain connected to the reference voltage output terminal; and
a fourth enhancement type NMOS transistor including:
a gate connected to a drain thereof and a gate of the third enhancement type NMOS transistor; and
a source connected to the ground terminal; and
the third depletion type NMOS transistor includes:
a gate connected to a source thereof and the drain of the fourth enhancement type NMOS transistor; and
a drain connected to the power supply terminal.
11. A reference voltage circuit according to claim 8 , wherein each of the first NMOS transistor and the second NMOS transistor is of an enhancement type.
12. A reference voltage circuit according to claim 8 , wherein:
the first NMOS transistor is of an enhancement type; and
the second NMOS transistor is of a depletion type.
13. A reference voltage circuit, comprising:
a first depletion type NMOS transistor including:
a gate connected to a source thereof a first terminal; and
a drain connected to a power supply terminal;
a second depletion type NMOS transistor including:
a gate connected to the gate of the first depletion type NMOS transistor;
a source connected to a second terminal; and
a drain connected to the power supply terminal;
a first NMOS transistor including:
a drain connected to the first terminal; and
a source connected to a ground terminal;
a second NMOS transistor including:
a gate connected to a drain thereof, a gate of the first NMOS transistor, and the second terminal; and
a source connected to a reference voltage output terminal,
the second NMOS transistor having a threshold voltage lower than a threshold voltage of the first NMOS transistor; and
a voltage generation circuit including a fifth enhancement type NMOS transistor, for generating a reference voltage between the reference voltage output terminal and the ground terminal.
14. A reference voltage circuit according to claim 13 , wherein the fifth enhancement type NMOS transistor includes:
a gate connected to the gate of the second NMOS transistor;
a source connected to the ground terminal; and
a drain connected to the reference voltage output terminal.
15. A reference voltage circuit according to claim 14 , further comprising a sixth enhancement type NMOS transistor including:
a gate connected to the gate of the fifth enhancement type NMOS transistor;
a source connected to the ground terminal; and
a drain connected to the source of the first NMOS transistor.
16. A reference voltage circuit according to claim 13 , wherein the fifth enhancement type NMOS transistor includes:
a gate connected to the reference voltage output terminal;
a drain connected to the reference voltage output terminal; and
a source connected to the ground terminal.
17. A reference voltage circuit according to claim 13 , wherein each of the first NMOS transistor and the second NMOS transistor is of an enhancement type.
18. A reference voltage circuit according to claim 13 , wherein:
the first NMOS transistor is of an enhancement type; and
the second NMOS transistor is of a depletion type.