IP Library Patent Application 12889582
Patent Application
App. No. 12/889,582

MULTILAYER CIRCUIT BOARD

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
12/889,582
Abstract

A multilayer circuit board includes a first dielectric layer, a second dielectric layer, a first conductor path, a second conductor path and a soldered joint. The first dielectric layer has a first side and a second side. The second dielectric layer has a first side and a second side, where the first side of the second dielectric layer facing towards the first side of the first dielectric layer. The first conductor path is disposed on the first side of the first dielectric layer. The second conductor path is disposed on the first side of the second dielectric layer. The soldered joint is disposed between the first dielectric layer and the second dielectric layer, where the soldered joint electrically connects the first conductor path to the second conductor path. The first dielectric layer extends continuously through an area surrounding the soldered joint.

Claims (31)

1 . A multilayer circuit board, comprising

a first dielectric layer having a first side and a second side;

a second dielectric layer having a first side and a second side, the first side of the second dielectric layer facing towards the first side of the first dielectric layer;

a first conductor path disposed on the first side of the first dielectric layer;

a second conductor path disposed on the first side of the second dielectric layer; and

a soldered joint disposed between the first dielectric layer and the second dielectric layer, where the soldered joint electrically connects the first conductor path to the second conductor path;

where the first dielectric layer extends continuously through an area surrounding the soldered joint.

2 . The multilayer circuit board of claim 1 , where the second dielectric layer extends continuously through the area surrounding the soldered joint.

3 . The multilayer circuit board of claim 1 , where the first conductor path and the second conductor path form an electric coil.

4 . The multilayer circuit board of claim 1 , where the solder joint includes solder that extends continuously from the first conductor path to the second conductor path.

5 . The multilayer circuit board of claim 1 , where at least one of

a first electric component is mounted to the second side of the first dielectric layer in the area surrounding the solder joint; and

a second electric component is mounted to the second side of the second dielectric layer in the area surrounding the solder joint.

6 . The multilayer circuit board of claim 1 , where a first metallization is disposed on the second side of the first dielectric layer;

7 . A method for producing a multilayer circuit board, comprising:

providing a first dielectric layer having a first side and a second side, and a first conductor path disposed on the first side of the first dielectric layer;

providing a second dielectric layer having a first side and a second side, and a second conductor path disposed on the first side of the second dielectric layer;

arranging the first dielectric layer and the second dielectric layer such that the first side of the second dielectric layer faces the first side of the first dielectric layer; and

forming an electrical connection between the first conductor path and the second conductor path using induction soldering.

8 . The method of claim 7 , further comprising:

predefining a first surface section on the first conductive path; and

predefining a second surface section on the second conductive path;

where the electrical connection is formed between the first surface section and the second surface section.

9 . The method of claim 8 , further comprising arranging the first surface section opposite to the second surface section.

10 . The method of claim 8 , further comprising disposing solder between the first surface section and the second surface section.

11 . The method of claim 8 , further comprising applying solder to at least one of the first surface section and the second surface section.

12 . The method of claim 8 , further comprising applying solder to the first surface section and the second surface section, where the solder on the first and the second surface sections is fused together during the step of induction soldering.

13 . The method of claim 7 , where at least one of the first dielectric layer and the second dielectric layer extends continuously through an area surrounding the electrical connection.

14 . The method of claims 13 , where in the area surrounding the solder joint at least one of

a first electric component is mounted to the second side of the first dielectric layer; and

a second electric component is mounted to the second side of the second dielectric layer.

Assignments (3)
RELEASE Recorded Nov 14, 2012
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: HARMAN INTERNATIONAL INDUSTRIES, INCORPORATED; HARMAN BECKER AUTOMOTIVE SYSTEMS GMBH
Reel/Frame 029294/0254 →
SECURITY AGREEMENT Recorded Feb 17, 2011
From: HARMAN INTERNATIONAL INDUSTRIES, INCORPORATED; HARMAN BECKER AUTOMOTIVE SYSTEMS GMBH
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025823/0354 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2010
From: SUZUKI, TSUNEO; DUPPER, ROLF
To: HARMAN BECKER AUTOMOTIVE SYSTEMS GMBH
Reel/Frame 025498/0365 →