Performing a multiply-multiply-accumulate instruction
In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple multipliers and adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to an absolute value for a pixel of a pixel block. Other embodiments are described and claimed.
1. An apparatus comprising:
a processor having a plurality of execution units, at least one of the execution units including a circuit comprising:
a first multiplier to multiply a first reference value with a first coefficient to obtain a first product;
a second multiplier to multiply a second reference value with a second coefficient to obtain a second product;
a first adder to combine the first and second products to obtain a first sum;
a second adder to combine the first sum and a third term to obtain a base value;
a third level of adders each to combine the base value with one of a plurality of representations of the first coefficient to obtain a first sum set; and
a fourth level of adders each to combine the first sum set with one of a plurality of representations of the second coefficient to obtain a second sum set, wherein the circuit is to populate a vector destination storage having a plurality of locations each to store an output of one of the third and fourth levels of adders.
2. The apparatus of claim 1 , wherein each location of the plurality of locations corresponds to a pixel of a pixel block.
3. The apparatus of claim 1 , wherein the circuit is part of a multiply-accumulate (MAC) unit.
4. The apparatus of claim 1 , wherein the circuit is to populate the vector destination storage responsive to a user-level multiply-multiply-add instruction.
5. The apparatus of claim 4 , wherein the circuit is to receive the first and second reference values and the third term associated with the user-level multiply-multiply-add instruction.
6. The apparatus of claim 5 , wherein the processor further includes a front end unit to receive the first and second reference values and the user-level multiply-multiply-add instruction.
7. The apparatus of claim 4 , wherein the circuit is to perform two multiplication operations and greater than 16 addition operations responsive to the user-level multiply-multiply-add instruction.
8. A method comprising:
receiving a dual multiply-add instruction in a front end unit of a processor;
decoding the dual multiply-add instruction and sending the decoded instruction and operands therefore to an execution unit of the processor; and
executing the decoded instruction in the execution unit, including performing a plurality of multiplication operations, first and second additions to obtain a base value, manipulating the base value in a first set of adders to obtain intermediate sum values, manipulating each of the intermediate sum values in a second set of adders to obtain final sum values, and storing at least the intermediate sum values and final sum values in a destination storage.
9. The method of claim 8 , wherein performing the plurality of multiplication operations includes:
performing a first multiplication of a first operand and a first coefficient to obtain a first product; and
performing a second multiplication of a second operand and a second coefficient to obtain a second product.
10. The method of claim 9 , wherein performing the first addition comprises combining the first product and the second product to obtain a first sum.
11. The method of claim 10 , wherein performing the second addition comprises combining the first sum and a third term to obtain the base value.
12. The method of claim 11 , wherein manipulating the base value includes performing addition operations between the base value and the first coefficient, a negative value of the first coefficient, and twice the first coefficient, to obtain the intermediate sum values.
13. The method of claim 12 , wherein manipulating each of the intermediate sum values includes performing addition operations between each of the intermediate sum values and the second coefficient, a negative value of the second coefficient, and twice the second coefficient, to obtain the final sum values.
14. A system comprising:
a processor having a plurality of execution units, at least one of the execution units including a circuit comprising a multiply-accumulate (MAC) unit including a plurality of multipliers and a plurality of adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to a value for a pixel of a pixel block, wherein a number of the plurality of adders exceeds a number of pixels in the pixel block; and
a dynamic random access memory (DRAM) coupled to the processor.
15. The system of claim 14 , wherein the MAC unit is to perform a plurality of multiplication operations and a plurality of addition operations responsive to a single one of the user-level multiply-multiply-accumulate instruction.
16. The system of claim 15 , wherein the single instruction is associated with first and second reference elements, first and second coefficients, and a constant.
17. The system of claim 16 , wherein the MAC unit comprises:
a first multiplier to multiply the first reference element with the first coefficient to obtain a first product;
a second multiplier to multiply the second reference element with the second coefficient to obtain a second product;
a first adder to combine the first and second products to obtain a first sum; and
a second adder to combine the first sum and the constant to obtain a base value.
18. The system of claim 17 , wherein the MAC unit further comprises:
a third level of adders each to combine the base value with one of a plurality of representations of the first coefficient to obtain a first sum set, each of the first sum set corresponding to one of the absolute values; and
a fourth level of adders each to combine the first sum set with one of a plurality of representations of the second coefficient to obtain a second sum set, each of the second sum set corresponding to one of the absolute values.
19. The system of claim 17 , wherein the base sum corresponds to one of the absolute values.
20. The system of claim 15 , wherein the MAC unit is to perform the plurality of multiplication operations and more than X addition operations responsive to the single instruction, wherein X corresponds to a number of the plurality of elements of the destination storage, the MAC unit including more than X adders.