IP Library Granted Patent US 8,450,986
Granted Patent B2
US 8,450,986 · App. 12/891,341 · Granted May 28, 2013

Voltage regulator

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Quick Facts
Patent No.
US 8,450,986
App. No.
12/891,341
Granted
May 28, 2013
Kind
B2
Abstract

Provided is a voltage regulator capable of setting an accurate short-circuit current. Used as a circuit for determining a current value of a short-circuit current of an overcurrent protection circuit is not a resistor for converting current into voltage but a circuit for controlling in the form of current, that is, a circuit of an N-channel depletion type transistor including a gate and a drain that are connected to each other and operating in a non-saturated state. The N-channel depletion type transistor has process fluctuations that are linked with those of a detection transistor, and hence an accurate short-circuit current may be set without trimming.

Claims (28)

1. A voltage regulator, comprising:

an error amplifier circuit for amplifying and outputting a difference between a divided voltage determined by dividing an output voltage of an output transistor, and a reference voltage, to control a gate of the output transistor; and

an overcurrent protection circuit for detecting an overcurrent flowing into the output transistor to limit a current of the output transistor,

wherein the overcurrent protection circuit comprises:

a sense transistor controlled by an output voltage of the error amplifier circuit, for sensing an output current of the output transistor;

a first transistor comprising an N-channel depletion type transistor or an N-channel enhancement type transistor having a gate connected to a drain thereof and that operates in a non-saturated region, for generating a voltage based on a current flowing through the sense transistor; and

an output current limiting circuit controlled by the voltage generated by the first transistor, for limiting a gate voltage of the output transistor.

2. A voltage regulator according to claim 1 , wherein the N-channel depletion type transistor comprises:

a plurality of N-channel depletion type transistors connected in series; and

a fuse for trimming connected in parallel to each of the plurality of N-channel depletion type transistors.

3. A voltage regulator, comprising:

an error amplifier circuit for amplifying and outputting a difference between a divided voltage determined by dividing an output voltage of an output transistor, and a reference voltage, to control a gate of the output transistor; and

an overcurrent protection circuit for detecting an overcurrent flowing into the output transistor to limit a current of the output transistor,

wherein the overcurrent protection circuit comprises:

a sense transistor controlled by an output voltage of the error amplifier circuit, for sensing an output current of the output transistor;

a first transistor that operates in a non-saturated region, for generating a voltage based on a current flowing through the sense transistor, wherein a source of the sense transistor is connected to a drain of the first transistor; and

an output current limiting circuit controlled by the voltage generated by the first transistor, for limiting a gate voltage of the output transistor.

4. A voltage regulator according to claim 1 ,

wherein the voltage regulator further comprises a resistor connected to a source of the N-channel enhancement type transistor.

5. A voltage regulator according to claim 1 ,

wherein the voltage regulator further comprises a second N-channel depletion type transistor connected to a source of the N-channel enhancement type transistor, the second N-channel depletion type transistor including a gate and a drain that are connected to each other.

6. A voltage regulator according to claim 1 ,

wherein the output current limiting circuit comprises a second transistor for detecting the voltage generated by the first transistor, and

wherein the second transistor comprises an initial transistor.

7. A voltage regulator according to claim 6 ,

wherein the output current limiting circuit further comprises a third transistor connected to a drain of the second transistor, and

wherein the third transistor comprises a P-channel transistor including a gate connected to a drain of the P-channel transistor.

8. A voltage regulator according to claim 3 , wherein the first transistor comprises an N-channel enhancement type transistor including a gate connected to a constant voltage circuit.

Assignments (5)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2010
From: IMURA, TAKASHI; SUZUKI, TERUO; NAKASHIMO, TAKAO; NIHEI, YOTARO
To: SEIKO INSTRUMENTS INC.
Reel/Frame 025047/0569 →