DC-DC conversion for a power amplifier using the RF input
A power amplifier system is provided that includes a power amplifier configured to receive an RF input. A DC-DC converter is coupled to the power amplifier. Clocking circuits drive the DC-DC converter. The clocking circuits use the RF input to generate a clock. The clock acts with the DC-DC converter to provide an output voltage used in the power amplifier.
1. A power amplifier system, comprising:
a power amplifier configured to receive an RF input;
a DC-DC converter coupled to the power amplifier; and
clocking circuits that drives the DC-DC converter, the clocking circuits using the RF input to generate a clock, the clock acting with the DC-DC converter to provide an output voltage used in the power amplifier, wherein divider ratios are changed to change a frequency of the clock to minimize interference.
2. A power amplifier system, comprising:
a power amplifier configured to receive an RF input;
a DC-DC converter coupled to the power amplifier; and
clocking circuits that drives the DC-DC converter, the clocking circuits using the RF input to generate a clock, the clock being generated from an RF signal present at an intermediate node or an output of the power amplifier, wherein the clock is between high and low bands of the power amplifier to minimize the clock interference of the high and low bands.
3. The system of claim 1 , wherein the clocking circuits square up the RF input to generate the clock.
4. The system of claim 1 , further comprising:
a multiple stage buffer coupled to the clock, the multiple stage buffer squaring up the clock and providing isolation between the clocking circuits and the RF input.
5. The system of claim 1 , further comprising:
a buck type switching regular controlled by the clock.
6. The system of claim 1 , further comprising:
a boost type switching regulator controlled by the clock.
7. The system of claim 1 , further comprising:
a buck boost type switching regulator controlled by the clock.
8. The system of claim 1 , further comprising:
a charge pump controlled by the clock.
9. The system of claim 1 , wherein DC generation is provided by a rectified version of the RF.
10. The system of claim 1 , wherein the RF input is divided down to provide the clock at a sub-harmonic.
11. The system of claim 1 , further comprising:
an injection locked oscillator centered at a fundamental of a frequency in a middle of a band of the power amplifier that provides the clock locked to the RF input.
12. The system of claim 1 , further comprising:
an injection locked oscillator; and
a divider, the injection locked oscillator providing an input to the divider to provide a divided down version of the clock at any harmonic of the fundamental frequency of the RF input.
13. The system of claim 1 , further comprising:
an injection locked oscillator; and
a divider, the injection locked oscillator providing an input to the divider to provide a divided down version of the clock at a fundamental frequency of the RF input.
14. The system of claim 1 , further comprising:
an injection locked oscillator centered at a harmonic of a frequency in a middle of a band of the power amplifier to provide the clock locked to the RF input.
15. The system of claim 1 , further comprising:
an injection locked oscillator locked to a squared up version of the RF input.
16. The system of claim 1 , further comprising:
a phase locked loop, PLL; and
a voltage controlled oscillator, VCO, wherein the VCO is locked to the RF input using the PLL.
17. The system of claim 1 , further comprising:
a frequency locked looped FLL; and
a VCO, wherein the VCO is locked to the RF input using the FLL.
18. The system of claim 1 , further comprising:
a delayed lock loop, DLL; and
a VCO, wherein the VCO is locked to the RF input using the DLL.
19. The system of claim 1 , further comprising:
a PLL; and
a VCO, wherein the VCO is locked to a divided down version of the RF input using the PLL.
20. The system of claim 1 , further comprising:
a FLL; and
a VCO, wherein the VCO is locked to a divided down version of the RF input using the FLL.
21. The system of claim 1 , further comprising:
a DLL; and
a VCO, wherein the VCO is locked to a divided down version of the RF input using the DLL.
22. The system of claim 1 , further comprising:
a VCO, wherein the RF input and the VCO are divided down to provide a frequency at which the VCO is operating at a fraction of an RF input frequency.
23. A power amplifier system, comprising:
a power amplifier configured to receive an RF input;
a DC-DC converter coupled to the power amplifier; and
clocking circuits that drives the DC-DC converter, the clocking circuits using the RF input to generate a clock, the clock being generated from an RF signal present at an intermediate node or an output of the power amplifier, wherein divider ratios are changed to change a frequency of the clock to minimize interference.
24. A power amplifier system, comprising:
a power amplifier configured to receive an RF input;
a DC-DC converter coupled to the power amplifier; and
clocking circuits that drives the DC-DC converter, the clocking circuits using the RF input to generate a clock, the clock acting with the DC-DC converter to provide an output voltage used in the power amplifier, wherein the clock is between high and low bands of the power amplifier to minimize the clock interference of the high and low bands.
25. The system of claim 1 , further comprising:
A digital serial interface that controls the clock.
26. The system of claim 1 , further comprising:
an LC based oscillator.
27. The system of claim 1 , further comprising:
a ring oscillator.
28. The system of claim 1 , further comprising:
an RC based oscillator.