Solid-state imaging device and manufacturing method for the same

1. A MOS solid-state imaging device comprising:

a semiconductor substrate provided with a pair of source and drain regions in a pixel area thereof, the pair of source and drain regions constituting part of a transistor in the pixel area;

an insulating film formed over the semiconductor substrate;

a wiring layer formed over the insulating film; and

a contact plug penetrating through the insulating film to connect either one of the pair of source and drain regions with the wiring layer, wherein

a surface area of said one of the pair of source and drain regions is silicided, the surface area contacting with the contact plug, and

a width of the surface area is equal to a width of the contact plug, and

wherein the semiconductor substrate is further provided with another pair of source and drain regions in a peripheral circuit area around the pixel area, the other pair of source and drain regions constituting part of another transistor in the peripheral circuit area,

the MOS solid-state imaging device further comprises another contact plug penetrating through the insulating film to connect either one of the other pair of source and drain regions with the wiring layer,

a surface area of said one of the other pair of source and drain regions is silicided, the surface area contacting with the other contact plug, and

a thickness of the surface area contacting with the contact plug is less than a thickness of the surface area contacting with the other contact plug.

2. The MOS solid-state imaging device of claim 1 , wherein the surface area contacting with the contact plug and the surface area contacting with the other contact plug are nickel silicide areas.

3. A manufacturing method for a MOS solid-state imaging device, comprising:

a first step of forming, in a pixel area of a semiconductor substrate, a first pair of source and drain regions of a first transistor, while forming, in a peripheral circuit area around the pixel area, a second pair of source and drain regions of a second transistor;

a second step of forming a silicide block film over the pixel area of the semiconductor substrate;

a third step of forming a first metal film over the semiconductor substrate to cover the silicide block film;

a fourth step of causing silicidation on a surface of at least one of the second pair of source and drain regions of the second transistor, by subjecting the semiconductor substrate to heat treatment;

a fifth step of forming an insulating film over the semiconductor substrate after removing a residue of the first metal film and the silicide block film;

a sixth step of forming a first contact hole in the insulating film above said at least one of the first pair of source and drain regions, while forming a second contact hole in the insulating film above said at least one of the second pair of source and drain regions;

a seventh step of forming a second metal film over an inner surface of the first contact hole and an inner surface of the second contact hole;

an eighth step of subjecting the semiconductor substrate to heat treatment to silicide a first surface area of said at least one of the first pair of source and drain regions, the first surface area exposed through the first contact hole, and to silicide a second surface area of said at least one of the second pair of source and drain regions, the second surface area exposed through the second contact hole; and

a ninth step of forming a first contact plug contacting with the first surface area by implanting a conductive material into the first contact hole, while forming a second contact plug contacting with the second surface area by implanting a conductive material into the second contact hole, after removing a residue of the second metal film.