Multi-stage GLONASS/GPS automatic frequency control
View Patent ↗A method of providing automatic frequency control pull-in for efficient receipt of GLONASS bits is described. This method can include first determining whether a channel noise (CNo) is greater than or equal to a predetermined value. When the CNo is greater than or equal to the predetermined value, the pull-in can be performed using a first series of predetection integration periods (PDIs) with activated decision-directed flips (DDFs) until a 20 ms boundary of a GLONASS data bit is found. When the CNo is less than the predetermined value, the pull-in can be performed using a second series of PDIs with always deactivated DDFs. A similar method of providing automatic frequency control pull-in for efficient receipt of GPS bits is also described.
1. A method of providing automatic frequency control pull-in for receipt of GLONASS bits, the method comprising:
determining, with a GLONASS receiver, whether a channel signal to noise ratio (CNo) is greater than or equal to a predetermined value; and
when the CNo is greater than or equal to the predetermined value, performing pull-in using a first series of predetection integration periods (PDIs) with an integrator, and activating decision-directed flips (DDFs) until a 20 ms boundary of a GLONASS data bit is found, wherein the activated DDFs adjust polarities of a first value and a second value, which are provided by a real component generator and an imaginary component generator, respectively, based, at least in part, on an output of the integrator.
2. The method of claim 1 , wherein using the first series of PDIs and activated DDFs includes proceeding to a next step only when predetermined conditions are met.
3. The method of claim 2 , wherein an initial step includes a PDI of 1 ms.
4. The method of claim 3 , wherein the initial step transitions to a first step when a test condition is met, and wherein the test condition includes satisfying a dot count test and a transition decision test using frequency error estimation.
5. The method of claim 4 , wherein the first step includes a PDI of 2 ms.
6. The method of claim 5 , wherein the first step transitions to a second step when the test condition is met.
7. The method of claim 6 , wherein the second step includes a PDI of 5 ms.
8. The method of claim 7 , wherein the second step transitions to a third step when the test condition is met and a 10 ms GLONASS bit boundary is detected.
9. The method of claim 8 , wherein the third step includes a PDI of 10 ms.
10. The method of claim 9 , wherein the third step transitions to a fourth step when the 20 ms GLONASS bit boundary is found.
11. The method of claim 10 , wherein the fourth step includes deactivating the DDFs.
12. The method of claim 1 , wherein when the CNo is less than the predetermined value, using a second series of PDIs with always deactivated DDFs.
13. The method of claim 12 , wherein performing the second series of PDIs and deactivated DDFs includes proceeding to a next step only when predetermined conditions are met.
14. The method of claim 13 , wherein an initial step includes a PDI of 2 ms.
15. The method of claim 14 , wherein the initial step transitions to a first step when a test condition is met and a 10 ms GLONASS bit boundary is detected, wherein the test condition includes a frequency lock test.
16. The method of claim 15 , wherein a first step includes a PDI of 5 ms.
17. The method of claim 16 , wherein the first step transitions to a second step when the test condition is met and the 20 ms GLONASS bit boundary is detected.
18. The method of claim 17 , wherein the second step includes a PDI of 10 ms.
19. A method of providing automatic frequency control pull-in for receipt of GPS bits, the method comprising:
determining, with a GPS receiver, whether a channel signal to noise ratio (CNo) is greater than or equal to a first predetermined value; and
when the CNo is greater than or equal to the first predetermined value, performing pull-in using a first series of predetection integration periods (PDIs) with an integrator, and activating decision-directed flips (DDFs) until a bit synchronization is achieved, wherein the activated DDFs adjust polarities of a first value and a second value, which are provided by a real component generator and an imaginary component generator, respectively, based, at least in part, on an output of the integrator.
20. The method of claim 19 , wherein using the first series of PDIs and activated DDFs includes proceeding to a next step only when predetermined conditions are met.
21. The method of claim 20 , wherein an initial step includes a PDI of 1 ms.
22. The method of claim 21 , wherein the initial step transitions to a first step when a test condition is met, and wherein the test condition includes satisfying a dot count test and a transition decision test using frequency error estimation.
23. The method of claim 22 , wherein the first step includes a PDI of 2 ms.
24. The method of claim 23 , wherein the first step transitions to a second step when the test condition is met.
25. The method of claim 24 , wherein the second step includes a PDI of 5 ms.
26. The method of claim 25 , wherein the second step transitions to a third step when the test condition is met and the bit synchronization is achieved.
27. The method of claim 26 , wherein the third step includes a PDI of 10 ms and deactivating the DDFs.
28. The method of claim 27 , wherein preceding the initial step, further including determining whether the CNo is greater than a second predetermined value, which is higher than the first predetermined value.
29. The method of claim 28 , wherein when the CNo is greater than the second predetermined value, then proceeding to the initial step.
30. The method of claim 28 , wherein when the CNo is less than or equal to the second predetermined value, then further including determining whether the CNo is greater than or equal to a third predetermined value, which is between the first predetermined value and the second predetermined value.
31. The method of claim 30 , wherein when the CNo is greater than or equal to the third predetermined value, then proceeding to the first step.
32. The method of claim 30 , wherein when the CNo is less than the third predetermined value, then proceeding to the second step.
33. The method of claim 19 , wherein when the CNo is less than the first predetermined value, using a second series of PDIs with always deactivated DDFs.
34. The method of claim 33 , wherein performing the second series of PDIs and deactivated DDFs includes proceeding to a next step only when predetermined conditions are met.
35. The method of claim 34 , wherein an initial step includes a PDI of 2 ms.
36. The method of claim 35 , wherein the initial step transitions to a first step when a test condition is met and a bit synchronization is achieved, wherein the test condition includes a frequency lock test.
37. The method of claim 36 , wherein the first step includes a PDI of 5 ms.
38. The method of claim 37 , wherein the first step transitions to a second step when the test condition is met.
39. The method of claim 38 , wherein the second step includes a PDI of 10 ms.
40. A method of providing automatic frequency control pull-in for receipt of GLONASS or GPS bits, the method comprising:
determining, with a receiver, whether a channel signal to noise ratio (CNo) is greater than or equal to a predetermined value;
when the CNo is greater than or equal to the predetermined value, performing pull-in using a first series of predetection integration periods (PDIs) with an integrator, and activating decision-directed flips (DDFs), wherein the activated DDFs adjust polarities of a first value and a second value, which are provided by a real component generator and an imaginary component generator, respectively, based, at least in part, on an output of the integrator; and
when the CNo is less than the predetermined value, performing pull-in using a second series of PDIs with the integrator, and deactivating the DDFs.