IP Library Granted Patent US 8,258,869
Granted Patent B2
US 8,258,869 · App. 12/894,144 · Granted Sep 4, 2012

Low noise amplifier with current bleeding branch

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Quick Facts
Patent No.
US 8,258,869
App. No.
12/894,144
Granted
Sep 4, 2012
Kind
B2
Abstract

An LNA circuit for providing a wide range of gain while maintaining the output headroom. In a radio frequency (RF) receiver, the signal received by the receiver may be extremely small. For a transmitter in a short distance, the received signal may be relatively strong. A low power amplifier usually is used to amplify the input signal. The LNA has to be designed to accommodate a wide range of gain. A convention LNA circuit supporting a wide range of gain often suffers from reduced output headroom due to increased current through the load resistor. The present invention discloses the use of current bleeding branch to allow a portion of current to flow through the current bleeding branch and consequently reduces the current that would have flown through the load resistor. Consequently, the voltage across the load resistor may be maintained low to allow adequate output headroom.

Claims (35)

1. A low-noise amplifier comprising:

an input transconductance stage that receives an input voltage signal;

a cascode transistor pair that is coupled to the input transconductance stage to generate an amplified output signal; and

an output load stage coupled to the amplified output signal, wherein the output load stage comprises a first load resistor coupled to an adjustable current source branch in parallel; and

wherein the output load stage further comprises a switchable branch coupled to the first load resistor and the adjustable current source branch in parallel, wherein the switchable branch comprises a second load resistor connected to a load switch in serial to select a gain mode.

2. A low-noise amplifier comprising:

an input transconductance stage that receives an input voltage signal;

a cascode transistor pair that is coupled to the input transconductance stage to generate an amplified output signal; and

an output load stage coupled to the amplified output signal, wherein the output load stage comprises a first load resistor coupled to an adjustable current source branch in parallel;

wherein the adjustable current source branch comprises a current mirror load transistor pair; and

wherein the adjustable current source branch further comprises a first degeneration resistor connected to the current mirror load transistor in serial.

3. The low-noise amplifier of claim 2 , wherein the output load stage further comprises a control transistor to supply a control signal to a gate of the current mirror load transistor pair to adjust a first current sourced by the current mirror load transistor pair, wherein source current of the control transistor is controlled by a control current.

4. The low-noise amplifier of claim 3 , wherein the control transistor is connected to a second degeneration resistor in serial.

5. A method for gain adjustable low-noise amplifier, the method comprising:

providing an input transconductance stage to receive an input voltage signal;

coupling a cascode transistor pair to the input transconductance stage to generate an amplified output signal;

coupling a first load resistor to the amplified output signal;

coupling an adjustable current source branch to the first load resistor in parallel;

adjusting DC operation point of the amplified output signal according to a change of equivalent resistance associated with the load resistor and the adjustable current source branch to obtain a desired gain of the low-noise amplifier, wherein the adjustable current source branch comprises a current mirror load transistor pair having a gate coupled to a control signal for adjusting first current of the current mirror load transistor pair; and

providing a switchable impedance branch coupled to the first load resistor in parallel to select a gain mode.

6. The method of claim 5 , further comprising:

providing a control transistor to generate the control signal coupled to the gate adjusting first current sourced by the current mirror load transistor pair.

7. The method of claim 6 , further comprising:

providing a control current to the control transistor to generate the control signal.

8. A method for gain adjustable low-noise amplifier, the method comprising:

providing an input transconductance stage to receive an input voltage signal;

coupling a cascode transistor pair to the input transconductance stage to generate an amplified output signal;

coupling a first load resistor to the amplified output signal;

coupling an adjustable current source branch to the first load resistor in parallel;

adjusting DC operation point of the amplified output signal according to a change of equivalent resistance associated with the load resistor and the adjustable current source branch to obtain a desired gain of the low-noise amplifier, wherein the adjustable current source branch comprises a current mirror load transistor pair having a gate coupled to a control signal for adjusting first current of the current mirror load transistor pair; and

providing a first degeneration resistor coupled to the current mirror load transistor to reduce noise associated with the current mirror load transistor pair and increase output resistance of the current mirror load transistor pair.

9. The method of claim 8 , further comprising:

providing a control transistor to generate the control signal coupled to the gate adjusting first current sourced by the current mirror load transistor pair.

10. The method of claim 9 , further comprising:

providing a control current to the control transistor to generate the control signal.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2015
From: QUINTIC MICROELECTRONICS (WUXI) CO., LTD.
To: NXP B.V.
Reel/Frame 034854/0262 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2015
From: NXP B.V.
To: QUINTIC MICROELECTRONICS (WUXI) CO., LTD.
Reel/Frame 034752/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2015
From: NXP B.V.
To: QUINTIC MICROELECTRONICS (WUXI) CO., LTD.
Reel/Frame 034747/0893 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2014
From: QUINTIC HOLDINGS
To: QUINTIC MICROELECTRONICS (WUXI) CO., LTD.
Reel/Frame 034037/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2010
From: ZHAO, ZHONGWU; JIN, XIAODONG
To: QUINTIC HOLDINGS
Reel/Frame 025091/0760 →