TEST CIRCUIT UNDER PAD
Aspects of the present invention relate to the arrangement of points of interconnection of integrated circuit die to the package in which they are enclosed. More specifically, aspects of the present invention pertain to an arrangement of bond pads over the active circuitry of an integrated circuit die, in order to permit a reduction in size of the die. An embodiment of the present invention may place a first bond pad over the active area of an integrated circuit, wherein the first bond pad is electrically coupled to a second bond pad outside of the active area of the integrated circuit. Production and delivery of the integrated circuit may proceed using the second bond pad during packaging, in parallel with the testing of packaging using the first bond pad. When processes related to the use of the first bond pad have been proven successful and sustainable, the second bond pad may be eliminated, resulting in a reduction of the size of the integrated circuit device. This approach may be employed to save die area, increasing the number of devices that may be produced on a silicon wafer, resulting in a reduction in device cost. The approach of the present invention works well whether the chip is pad or core limited. Although reference has been made to the used of this technique on a silicon wafer, an embodiment of the present invention may be employed in the fabrication of integrated circuit device using other materials as well, without departing from the spirit and scope of the present invention.
1 - 13 . (canceled)
14 . A method of manufacturing an integrated circuit (IC) device comprising a core area and a first plurality of bond pads disposed over at least one active circuit component, the method comprising:
i) creating layout information representing at least the core area, the first plurality of bond pads, and a second plurality of bond pads disposed over an area of the device that is free of active circuit components;
ii) packaging a first portion of a fabricated integrated circuit (IC) die using the first plurality of bond pads;
iii) testing the first portion to determine whether use of the first plurality of bond pads is successful;
iv) modifying the layout information to remove the second plurality of bond pads, if testing is successful;
v) revising the layout information, if testing is not successful; and
vi) repeating (ii) through (v) until testing is successful.
15 . The method according to claim 14 , further comprising:
vii) packaging a second portion of the fabricated die using the second plurality of bond pads; and
viii) delivering the packaged second portion to a user.
16 . The method according to claim 14 wherein the integrated circuit device comprises silicon.
17 . The method according to claim 14 wherein the packaging comprises bonding a conductor to at least one bond pad.
18 . The method according to claim 17 wherein the bonding comprises pressure bonding.
19 . The method according to claim 14 wherein active circuit components comprise one of a transistor, a diode, a resistor, a capacitor, an inductor, and a conductive path.
20 . The method according to claim 14 wherein each of the plurality of second bond pads is connected by a conductive path to a corresponding one of the first plurality of bond pads.
21 . The method according to claim 14 , further comprising:
vii) packaging die using the first plurality of bond pads, if testing is successful; and
viii) delivering the die packaged using the first plurality of bond pads to a user.
22 . The method according to claim 14 further comprising fabricating the integrated circuit (IC) die using the layout information.