Granted Patent B2

US 9,003,159 · App. 12/898,483 · Granted Apr 7, 2015

Inventors: Shekhar S. Deshkar (Pune, IN); Sandeep Karmarkar (Pune, IN); Arvind Pruthi (Los Gatos, CA); Ram Kishore Johri (San Jose, CA)

Assignee: Marvell World Trade Ltd.

G06F12/0873G06F12/0246G06F12/0292G06F2212/222G06F2212/261

Abstract

Claims (33)

1. An apparatus, comprising:

a flash memory structure;

circuitry to receive a command sequence that includes a logical address, wherein the logical address includes (i) information that identifies a data storage device from among two or more separate data storage devices and (ii) a logical page number within the identified data storage device;

circuitry to receive data associated with the logical address;

circuitry to allocate a physical page in the flash memory structure;

circuitry to store a mapping from the logical address to a physical address associated with the physical page;

circuitry to write, based on the physical address, the data associated with the logical address to the flash memory structure to cache the data associated with the logical address; and

circuitry to (i) invalidate the physical page in the flash memory structure based on the logical address being included in an invalidate command sent by an application to indicate caching of the data associated with the logical address is no longer needed and (ii) allow a garbage collector to directly use the physical page when performing an erasure to make the physical page available for re-allocation;

wherein the mapping indicates a cached status of the data associated with the logical address; and

wherein the mapping goes from the logical address to the physical address without an intervening reference to a logical page number (LPN) of the flash memory structure.

2. The apparatus of claim 1 , comprising:

circuitry to receive a read command sequence that includes a logical address;

circuitry to identify a physical address associated with the logical address of the read command sequence; and

circuitry to read, based on the identified physical address, data from the flash memory structure to provide cached data associated with the logical address of the read command sequence.

3. The apparatus of claim 1 , wherein the flash memory structure is used as a write-back cache, has less than 25% of its total capacity reserved specifically for garbage collection, and has less than 40% of its total capacity reserved for both garbage collection and buffer space.

4. The apparatus of claim 1 , wherein the flash memory structure comprises two or more cache devices, and wherein the circuitry to allocate comprises circuitry to select a cache device from among the two or more cache devices based on the logical address.

5. The apparatus of claim 4 , wherein the circuitry to select comprises circuitry to apply a hash function to a {target-ID, offset, length} tuple to produce an identifier of the cache device from among the two or more cache devices.

6. A method, comprising:

receiving, from a host system, information that includes a logical address, wherein the logical address comprises (i) a target device identifier for one of two or more separate data storage devices and (ii) a logical block address (LBA) within a single data storage device identified by the target device identifier;

receiving data associated with the logical address from one of the host system or a data storage device of the two or more separate data storage devices;

allocating a physical page in a flash memory structure, wherein the flash memory structure is configured to cache data for the two or more separate data storage devices;

storing a mapping from the logical address to a physical address of the physical page;

writing, based on the physical address, the data associated with the logical address to the flash memory structure to cache the data associated with the logical address;

invalidating the physical page in the flash memory structure based on the logical address being included in an invalidate command sent by an application to indicate caching of the data associated with the logical address is no longer needed; and

allowing a garbage collector to directly use the physical page when performing an erasure to make the physical page available for re-allocation;

wherein the mapping indicates a cached status of the data associated with the logical address; and

wherein the mapping goes directly from the logical address to the physical address.

7. The method of claim 6 , wherein receiving data associated with the logical address comprises reading data from the single data storage device based on the logical address.

8. The method of claim 6 , wherein the flash memory structure is used as a write-back cache, has less than 25% of its total capacity reserved specifically for garbage collection, and has less than 40% of its total capacity reserved for both garbage collection and buffer space.

9. The method of claim 6 , wherein the flash memory structure comprises two or more caching devices, the method comprising:

selecting a caching device from among the two or more caching devices based on the logical address, wherein writing data to the flash memory structure comprises communicating with the selected caching device.

10. The method of claim 9 , wherein selecting the caching device comprises applying a hash function to a {target-ID, offset, length} tuple to produce an identifier of the caching device from among the two or more caching devices.

11. The method of claim 6 , wherein the two or more separate data storage devices comprise two or more hard disk drives.

Assignments (9)

Continuity (2)