Semiconductor device and structure
View Patent ↗A semiconductor device including a first single crystal layer with first transistors and a first alignment mark; at least one metal layer overlying the first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer including activated dopant regions, the second layer overlying the at least one metal layer, wherein the second layer includes second transistors, wherein the second transistors are processed aligned to the first alignment mark with less than 100 nm alignment error, and the second transistors include mono-crystal, horizontally-oriented transistors.
1. A semiconductor device comprising:
a first single crystal layer comprising first transistors and a first alignment mark;
at least one metal layer overlying said first single crystal layer, wherein said at least one metal layer comprises copper or aluminum; and
a second layer comprising activated dopant regions, said second layer overlying said at least one metal layer, wherein said second layer comprises second transistors, wherein said second transistors are processed aligned to said first alignment mark with less than 100 nm alignment error, wherein said second transistors comprise mono-crystal, horizontally-oriented transistors.
2. A semiconductor device according to claim 1 , wherein said second transistors comprise P type transistors and N type transistors.
3. A mobile system comprising a semiconductor device according to claim 1 .
4. A semiconductor device according to claim 1 , wherein said second transistors form a plurality of logic gates.
5. A semiconductor device according to claim 1 , further comprising a heat spreader layer between said at least one metal layer and said second layer.
6. A semiconductor device according to claim 1 , further comprising at least one power grid comprising heat removal connections, wherein said power grid provides power to a plurality of said second transistors.
7. A semiconductor device according to claim 1 , wherein said second layer comprises a plurality of vias through said second layer, said plurality of vias providing connection of said first transistors to said second transistors.
8. A semiconductor device comprising:
a first single crystal layer comprising first transistors, and a first alignment mark;
at least one metal layer overlying said first single crystal layer, wherein said at least one metal layer comprises copper or aluminum; and
a second layer comprising activated dopant regions, said second layer overlying said at least one metal layer, wherein said second layer comprises second transistors, wherein said second transistors are processed aligned to said first alignment mark with less than 100 nm alignment error, said second transistors forming a plurality of logic gates;
wherein said second transistors are mono-crystal transistors.
9. A semiconductor device according to claim 8 , wherein said second transistors comprise P type transistors and N type transistors.
10. A mobile system comprising a semiconductor device according to claim 8 .
11. A semiconductor device according to claim 8 , wherein said second transistors comprise horizontally oriented transistors.
12. A semiconductor device according to claim 8 , further comprising a heat spreader layer between said at least one metal layer and said second layer.
13. A semiconductor device according to claim 8 , further comprising at least one power grid comprising heat removal connections, wherein said power grid provides power to a plurality of said second transistors.
14. A semiconductor device according to claim 8 , wherein said second layer comprises a plurality of vias through said second layer, said plurality of vias providing connection of said first transistors to said second transistors.
15. A semiconductor device comprising:
a first single crystal layer comprising first transistors and a first alignment mark;
at least one metal layer overlying said first single crystal layer, wherein said at least one metal layer comprises copper or aluminum;
a second layer overlying said at least one metal layer, wherein said second layer comprises a second alignment mark, second transistors, and a plurality of vias through said second layer, wherein said plurality of vias are aligned according to said first alignment mark and said second alignment mark;
wherein said second transistors are mono-crystal transistors.
16. A semiconductor device according to claim 15 , wherein said second transistors comprise P type transistors and N type transistors.
17. A mobile system comprising a semiconductor device according to claim 15 .
18. A semiconductor device according to claim 15 , wherein said second transistors comprise horizontally oriented transistors.
19. A semiconductor device according to claim 15 , further comprising a heat spreader layer between said at least one metal layer and said second layer.
20. A semiconductor device according to claim 15 , further comprising at least one power grid comprising heat removal connections, wherein said power grid provides power to a plurality of said second transistors.
21. A semiconductor device according to claim 15 , wherein said second transistors form a plurality of logic gates.
22. A semiconductor device according to claim 15 , wherein said plurality of vias through said second layer are aligned with less than 100 nm alignment error.