Thin film transistor and method of forming the same

1. A thin film transistor comprising:

a gate electrode;

an oxide semiconductor pattern;

a first gate insulating layer pattern between the gate electrode and the oxide semiconductor pattern

a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern, wherein the source electrode and the drain electrode are separated from each other; and

a first insulating layer pattern between the source electrode and the drain electrode, and the oxide semiconductor pattern, wherein the first insulating layer pattern partially contacts the source electrode and drain electrode and the first gate insulating layer pattern, and wherein the first insulating layer pattern is enclosed by an outer portion, wherein the outer portion includes a first step and a second step on the first step, and wherein the first and second steps positioned on the oxide semiconductor pattern are covered by the source and drain electrodes and wherein the first insulating layer pattern contacts a top surface of the oxide semiconductor pattern.

2. The thin film transistor of claim 1 , wherein the outer portion includes a layer comprising a high-molecule compound including carbon.

3. The thin film transistor of claim 1 , wherein the first gate insulating layer pattern is a silicon oxide layer.

4. The thin film transistor of claim 3 , wherein the gate electrode and the oxide semiconductor are separated from each other by a distance of more than at least 1000 Å.

5. The thin film transistor of claim 3 , wherein the first insulating layer pattern is a silicon oxide layer.

6. The thin film transistor of claim 5 , wherein a thickness of the first insulating layer is less than 3000 Å.

7. The thin film transistor of claim 5 , wherein the outer portion includes a layer made of a high-molecule compound including carbon.

8. The thin film transistor of claim 1 , further comprising:

a second gate insulating layer between the gate electrode and the oxide semiconductor pattern.

9. The thin film transistor of claim 8 , wherein the second gate insulating layer contacts the gate electrode, and wherein the second gate insulating layer is a silicon nitride layer.

10. The thin film transistor of claim 9 , wherein a thickness of the second gate insulating layer is more than 1000 Å.

11. A method for forming a thin film transistor comprising:

forming a gate electrode;

forming a first gate insulating layer on the gate electrode;

forming an oxide semiconductor pattern on the first gate insulating layer;

forming a first insulating layer pattern on the oxide semiconductor pattern, wherein the first insulating layer pattern partially contacts the first gate insulating layer;

continuously patterning the first gate insulating layer to form a first gate insulating layer pattern;

partially etching the first insulating layer pattern to form a second insulating layer pattern enclosed by an outer portion having a step shape; and

forming a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern, wherein the source electrode and the drain electrode partially contact the second insulating layer pattern and wherein the source electrode and the drain electrode are separated from each other, wherein the outer portion includes a first step and a second step on the first step, and wherein the first and second steps positioned on the oxide semiconductor pattern are covered by the source and drain electrodes and wherein the first insulating layer pattern contacts a to, surface of the oxide semiconductor pattern.

12. The method of claim 11 , wherein the first gate insulating layer pattern is a silicon oxide layer.

13. The method of claim 12 , wherein the second insulating layer pattern is a silicon oxide layer.

14. The method of claim 13 , wherein a thickness of the second insulating layer pattern is less than 3000 Å.

15. The method of claim 11 , wherein forming the first insulating layer pattern and forming the first gate insulating layer pattern includes performing a first etching process, wherein

a halogen carbon compound and oxygen gas are used as a main gas in the first etching process.

16. The method of claim 15 , wherein the main gas further includes a halogen-sulfur compound as the main gas, wherein the amount of the halogen-sulfur compound is 20% less than the amount of the halogen-carbon compound and oxygen gas.

17. The method of claim 16 , wherein the halogen-carbon compound is C 4 F 8 .

18. The method of claim 11 , wherein partially etching the first insulating layer pattern to form the second insulating layer pattern includes

removing a high-molecule compound formed on a surface of the first insulating layer pattern, wherein the high-molecule compound includes carbon, and

partially etching the first insulating layer pattern from which the high-molecule compound is removed, and forming a high-molecule compound including carbon on the outer portion.

19. The method of claim 18 , wherein removing the high-molecule compound includes performing a second etching process using an inert gas and oxygen as the main gas.

20. The method of claim 18 , wherein partially etching the first insulating layer pattern to form the high-molecule compound on the outer portion includes performing a third etching process using the halogen-carbon compound and oxygen gas as a main gas of the third etching process.

21. The method of claim 20 , wherein the amount of the halogen-carbon compound supplied for the third etching process is equal to or more than the amount of oxygen gas.

22. The method of claim 21 , wherein the halogen-carbon compound for the third etching process is C 4 F 8 .

23. The thin film transistor of claim 1 , wherein the first and second steps are formed along an entire outer circumference of the first insulating layer pattern.

24. The thin film transistor of claim 1 , wherein the first insulating layer does not include any contact hole.