Hysteretic controlled buck-boost converter
An apparatus includes a buck boost converter for generating a regulated output voltage responsive to an input voltage. The buck boost converter includes an inductor, a first pair of switching transistors responsive to a first PWM signal and a second pair of switching transistors responsive to a second PWM signal. An error amplifier generates an error voltage responsive to the regulated output voltage and a reference voltage. A control circuit generates the first PWM signal and the second PWM signal responsive to the error voltage and a sensed current voltage responsive to a sensed current through the inductor. The control circuit controls switching of the first pair of switching transistors and the second pair of switching transistors using the first PWM signal and the second PWM signal responsive to the sensed current through the inductor and a plurality of offset error voltages based on the error voltage.
1. An apparatus, comprising:
a buck boost converter for generating a regulated output voltage responsive to an input voltage, the buck boost converter including an inductor, a first pair of switching transistors responsive to a first PWM signal and a second pair of switching transistors responsive to a second PWM signal;
an error amplifier for generating an error voltage responsive to the regulated output voltage;
a control circuit for generating the first PWM signal and the second PWM signal responsive to the error voltage and a sensed current voltage responsive to a sensed current through the inductor; and
wherein the control circuit controls switching of the first pair of switching transistors and the second pair of switching transistors using the first PWM signal and the second PWM signal responsive to the sensed current through the inductor and a plurality of offset error voltages based on the error voltage.
2. The apparatus of claim 1 , wherein the control circuit further comprises:
summation circuitry for generating the plurality of offset error voltages responsive to the error voltage and a first offset voltage and a second offset voltage; and
voltage mode control circuitry for generating the first PWM signal and the second PWM signal responsive to comparison of the sensed current voltage with each of the plurality of offset error voltages.
3. The apparatus of claim 2 , wherein the voltage mode control circuitry further comprises:
a plurality of comparators, each of the comparators comparing the sensed current voltage with one of the plurality of offset error voltages to generate a voltage control signal;
a first latch circuit connected to receive a first pair of the voltage control signals and generate the first PWM signal responsive thereto; and
a second latch circuit connected to receive a second pair of the voltage control signals and generate the second PWM signal responsive thereto.
4. The apparatus of claim 2 , wherein in a buck mode of operation the first PWM signal alternately turns on and off each of the first pair of switching transistors responsive to the sensed current voltage either exceeding a first of the plurality of offset error voltages or falling below a second of the plurality of offset error voltages and the second PWM signal keeps turned off the one of the second pair of switching transistors and keeps turned on the other of the second pair of switching transistors.
5. The apparatus of claim 2 , wherein in a boost mode of operation the second PWM signal alternately turns on and off each of the second pair of switching transistors responsive to the sensed current voltage either exceeding a third of the plurality of offset error voltages or falling below a fourth of the plurality of offset error voltages and the first PWM signal keeps turned off one of the first pair of switching transistors and keeps turned on the other of the first pair of switching transistors.
6. The apparatus of claim 2 , wherein in a buck-boost mode of operation the first PWM signal alternatively turns on and off each of the first pair of switching transistors responsive to the sensed current voltage either exceeding the first of the plurality of offset error voltages or falling below the second of the plurality of offset error voltages while the second PWM signal alternatively turns on and off each of the second pair of switching transistors responsive to the sensed current voltage either exceeding the third of the plurality of offset error voltages or falling below the fourth of the plurality of offset error voltages.
7. A control circuit for controlling switching of a buck boost converter, comprising:
a first input for receiving a sensed current voltage responsive to a sensed current through an inductor of a buck boost converter;
a second input for receiving an error voltage from an error amplifier;
a pair of outputs for providing a first PWM signal and a second PWM signal;
a PWM control circuit for generating the first PWM signal and the second PWM signal responsive to the error voltage and a sensed current voltage responsive to a sensed current through the inductor; and
wherein the control circuit controls switching of the first pair of switching transistors and the second pair of switching transistors using the first PWM signal and the second PWM signal responsive to the sensed current through the inductor and a plurality of offset error voltages based on the error voltage.
8. The control circuit of claim 7 , wherein the control circuit further comprises:
summation circuitry for generating the plurality of offset error voltages responsive to the error voltage and a first offset voltage and a second offset voltage; and
a hysteretic voltage mode control circuitry for generating the first PWM signal and the second PWM signal responsive to comparison of the sensed current voltage with each of the plurality of offset error voltages.
9. The control circuit of claim 8 , wherein the hysteretic voltage mode control circuitry further comprises:
a plurality of comparators, each of the comparators comparing the sensed current voltage with one of the plurality of offset error voltages to generate a voltage control signal;
a first latch circuit connected to receive a first pair of the voltage control signals and generate the first PWM signal responsive thereto; and
a second latch circuit connected to receive a second pair of the voltage control signals and generate the second PWM signal responsive thereto.
10. The control circuit of claim 8 , wherein in a buck mode of operation the first PWM signal alternately turns on and off each of the first pair of switching transistors responsive to the sensed current voltage either exceeding a first of the plurality of offset error voltages or falling below a second of the plurality of offset error voltages and the second PWM signal keeps turned off the one of the second pair of switching transistors and keeps turned on the other of the second pair of switching transistors.
11. The control circuit of claim 8 , wherein in a boost mode of operation the second PWM signal alternately turns on and off each of the second pair of switching transistors responsive to the sensed current voltage either exceeding a third of the plurality of offset error voltages or falling below a fourth of the plurality of offset error voltages and the first PWM signal keeps turned off one of the first pair of switching transistors and keeps turned on the other of the first pair of switching transistors.
12. The control circuit of claim 8 , wherein in a boost mode of operation the second PWM signal alternately turns on and off each of the second pair of switching transistors responsive to the sensed current voltage either exceeding a third of the plurality of offset error voltages or falling below a fourth of the plurality of offset error voltages and the first PWM signal keeps turned off one of the first pair of switching transistors and keeps turned on the other of the first pair of switching transistors.
13. A method for controlling operations of a buck boost converter, comprising the steps of:
generating a regulated output voltage responsive to an input voltage;
generating an error voltage responsive to the regulated output voltage and a reference voltage;
generating a first PWM signal and a second PWM signal responsive to a sensed current through an inductor and a plurality of offset error voltages based on the error voltage; and
switching of a first pair of switching transistors and a second pair of switching transistors using the first PWM signal and the second PWM signal.
14. The method of claim 13 , wherein the step of generating the first PWM signal and the second PWM signal further comprises the steps of:
generating the plurality of offset error voltages responsive to the error voltage and a first offset voltage and a second offset voltage; and
comparing the sensed current voltage with each of the plurality of offset error voltage to generate the first PWM signal and the second PWM signal.
15. The method of claim 14 , further including the step of:
generating the first PWM signal responsive to a first pair of voltage control signals from the step of comparing; and
generating the second PWM signal responsive to a second pair of voltage control signals from the step of comparing.
16. The method of claim 13 , wherein the step of generating the first PWM signal and the second PWM signal further comprises the step of generating the first PWM signal and the second PWM signal in a buck mode of operation, further comprising the steps of:
alternately turning on and off each of the first pair of switching transistors responsive to the sensed current voltage either exceeding a first of the plurality of offset error voltages or falling below a second of the plurality of offset error voltages;
keeping turned off the one of the second pair of switching transistors; and
keeping turned on an other of the second pair of switching transistors. turning off the second pair of switching transistors.
17. The method of claim 13 , wherein the step of generating the first PWM signal and the second PWM signal further comprises the step of generating the first PWM signal and the second PWM signal in a boost mode of operation, further comprising the steps of:
alternately turning on and off each of the second pair of switching transistors responsive to the sensed current voltage either exceeding a third of the plurality of offset error voltages or falling below a fourth of the plurality of offset error voltages;
keeping turned off one of the first pair of switching transistors; and
keeping turned on an other of the first pair of switching transistors,
turning off the first pair of switching transistors.
18. The method of claim 13 , wherein the step of generating the first PWM signal and the second PWM signal further comprises the step of generating the first PWM signal and the second PWM signal in a buck-boost mode of operation, further comprising the steps of:
alternately turning on and off each of the first pair of switching transistors responsive to the sensed current voltage either exceeding a first of the plurality of offset error voltages or falling below a second of the plurality of offset error voltages; and
alternately turning on and off each of the second pair of switching transistors responsive to the sensed current voltage either exceeding a third of the plurality of offset error voltages or falling below a fourth of the plurality of offset error voltages.