IP Library Granted Patent US 9,154,126
Granted Patent B2
US 9,154,126 · App. 12/904,844 · Granted Oct 6, 2015

High voltage output driver

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Quick Facts
Patent No.
US 9,154,126
App. No.
12/904,844
Granted
Oct 6, 2015
Kind
B2
Abstract

An output driver circuit is provided. In accordance with various example embodiments, an output driver circuit includes a high-side driver circuit having transistors coupled in anti-series between a power source and an output node, and a low-side driver circuit having transistors coupled in anti-series between the output node and ground. For each transistor, a diode is connected between the source and drain of the transistor, with the diodes of the respective high-side and low-side circuits being arranged to prevent/mitigate the flow of current in opposite directions.

Claims (40)

1. A push-pull output driver circuit comprising:

a high-side driver circuit including two transistors connected between a power source and an output node, the transistors connected to one another in anti-series and responsive to a first control signal;

a low-side driver circuit including two transistors connected between the output node and ground, the transistors connected to one another in anti-series and responsive to a second control signal;

for the high-side driver circuit, a diode connected between the source and drain of one of the transistors, and another diode connected between the source and drain of the other one of the transistors, the respective diodes being configured and arranged to prevent current flow between the power source and output node in opposite directions;

for the low-side driver circuit, a diode connected between the source and drain of one of the transistors, and another diode connected between the source and drain of the other one of the transistors, the respective diodes being configured and arranged to prevent current flow between the output node and ground in opposite directions; and

wherein the high-side and low-side driver circuits respond to the first and second control signals for push-pull driving of the output node, wherein the high-side driver circuit further includes a charge pump configured to apply a voltage to short the gates and the connected source/drain active regions of the high-side driver circuit transistors.

2. A high voltage driver circuit comprising:

a power source;

a ground circuit;

an output node connected to a load;

a high-side driver circuit including two transistors connected in anti-series between the power source and the output node;

a low-side driver circuit including two transistors connected in anti-series between the output node and ground;

for the high-side driver circuit, a diode connected between the source and drain of one of the transistors, and another diode connected between the source and drain of the other one of the transistors, the respective diodes being configured and arranged to mitigate current flow between the power source and output node;

for the low-side driver circuit, a diode connected between the source and drain of one of the transistors, and another diode connected between the source and drain of the other one of the transistors, the respective diodes being configured and arranged to mitigate current flow between the output node and ground;

a control circuit including

a first circuit connected between ground and the high-side driver circuit and configured to provide a first signal to the high-side driver circuit to switch on the transistors of the high-side driver circuit, and

a second control circuit connected between the low-side driver circuit and the power source and configured to provide a second signal to the low-side driver circuit to switch on the transistors of the low-side driver circuit; and

wherein the output node is configured to provide an output signal to the load when the transistors of the high-side driver circuit or the transistors of the low-side driver circuit have been turned on.

3. The circuit of claim 2 , wherein each the transistors is respectively configured to operate in an on state to bypass the diode connected between the source and drain of the transistor.

4. The circuit of claim 2 , wherein

the high-side driver circuit includes

a first high-side transistor having a source/drain region connected to the power source,

a second high-side transistor having a source/drain region connected in anti-series with a source/drain region of the first high-side transistor that is not connected to the power source, and having another source/drain region connected to the output node, and

each high-side transistor having a gate/source region that is driven by a control circuit; and

the low-side driver circuit includes

a first low-side transistor having a source/drain region connected to the output node,

a second low-side transistor having a source/drain region connected in anti-series with a source/drain region of the first low-side transistor that is not connected to the output node, and having another source/drain region connected to the ground circuit, and

each low-side transistor having a gate/source region that is driven by a control circuit.

5. The circuit of claim 2 , wherein the two transistors of at least one of the high-side driver circuit and the low-side driver circuit are of the same conductivity type.

6. The circuit of claim 2 , wherein the transistors of the high-side driver circuit have a conductivity type that is opposite the conductivity type of the transistors of the low-side driver circuit.

7. The circuit of claim 2 , wherein the diodes of the high-side driver circuit are oriented in opposite directions relative to one another, and the diodes of the low-side driver circuit are oriented in opposite directions relative to one another, to respectively mitigate the passage of current between the output node and the power source on the high-side circuit, and between the output node and the ground circuit on the low-side circuit, when the transistors are in an off state.

8. An output driver circuit comprising:

a high-side driver circuit connected between a power source and an output for driving a load, and including transistors connected to one another in anti-series and in parallel with diodes, the diodes being arranged to mitigate the flow of current between the power source and the output via when the transistors are off;

a low-side driver circuit connected between the output and ground, and including transistors connected to one another in anti-series and in parallel with diodes, the diodes being arranged to mitigate the flow of current between the output and ground when the transistors are off; and

a control circuit including

a first circuit connected between the high-side driver circuit and ground and configured to switch the transistors of the high-side driver circuit on to drive the output high, and

a second circuit connected between the low-side driver circuit and the power source and configured and arranged to switch the transistors of the low-side driver circuit on to drive the output low.

9. The circuit of claim 8 , wherein

the diodes of the high-side output driver circuit are oriented in opposite directions relative to one another to mitigate the passage of current between the output and the power source, and

the diodes of the low-side output driver circuit are oriented in opposite directions relative to one another to mitigate the passage of current between the output and ground.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2011
From: NIEROP, PIETER GUSTAAF; DE HAAS, CLEMENS GERHARDUS JOHANNES; VAN DIJK, LUC
To: NXP, B.V.
Reel/Frame 026791/0372 →