IP Library Granted Patent US 8,476,614
Granted Patent B2
US 8,476,614 · App. 12/906,214 · Granted Jul 2, 2013

Memory device and fabrication process thereof

Inventors: Jun Sumino (Kanagawa, JP); Shuichiro Yasuda (Kanagawa, JP)
Assignee: Sony Corporation
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Quick Facts
Patent No.
US 8,476,614
App. No.
12/906,214
Granted
Jul 2, 2013
Kind
B2
Abstract

A memory device that includes a resistive-change memory element, the memory device includes: a first memory element that includes a first resistive-change layer and a first electrode connected to the first resistive-change layer; and a second memory element that includes a second resistive-change layer and a second electrode connected to the second resistive-change layer, wherein at least one of the thickness and the material of the second resistive-change layer and the area of the second electrode in contact with the second resistive-change layer is different from the corresponding one of the thickness and the material of the first resistive-change layer and the area of the first electrode in contact with the first resistive-change layer.

Claims (12)

1. A memory device that includes a resistive-change memory element, the memory device comprising:

a first memory element that includes a first resistive-change layer, a first resistance-change material supply layer and a first electrode connected to the first resistive-change layer; and

a second memory element that includes a second resistive-change layer, a second resistance-change supply layer and a second electrode connected to the second resistive-change layer,

wherein,

at least one of (a) the thickness of the second resistive-change layer and (b) the area of the second electrode in contact with the second resistive-change layer is different from the corresponding one of (a) the thickness of the first resistive-change layer and (b) the area of the first electrode in contact with the first resistive-change layer,

each of the first and second resistive-change layers is made of a material whose resistance changes when an amount of resistance-change material therein from its respective resistance-change supply material layer changes under the influence of a voltage across the resistance-change layer and its respective resistance-change material supply layer, and

the first and second memories have different rewrite speeds due to the difference.

2. The memory device according to claim 1 , wherein each resistance-change material supply layer is an ion supply layer, and the resistance-change material comprises ions.

3. The memory device according to claim 2 , wherein the resistive-change material supply layer includes at least one kind of element selected from S, Se, and Te, and at least one kind of element selected from Zr, Cu, and Ag.

4. The memory device according to claim 1 , wherein the thickness and the material of the second resistive-change layer are respectively different from the thickness and the material of the first resistive-change layer.

5. The memory device according to claim 1 , wherein the first resistive-change layer and the second resistive-change layer are formed of a material selected from tungsten oxide, Ta 2 O 5 , Al 2 O 3 , SiO 2 , NiO, CoO, CeO 2 , and HfO 2 .

6. The memory device according to claim 1 , wherein at least one kind of element selected from zirconium, silicon, oxygen, and noble metal is introduced to the second resistive-change layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2010
From: SUMINO, JUN; YASUDA, SHUICHIRO
To: SONY CORPORATION
Reel/Frame 025149/0883 →
Priority Claims (1)
JP 2009-245597 · Oct 26, 2009 · national
Continuity (1)
Related Publication 20110095255A1 · Apr 28, 2011