IP Library Granted Patent US 8,907,987
Granted Patent B2
US 8,907,987 · App. 12/908,365 · Granted Dec 9, 2014

System and method for downsizing video data for memory bandwidth optimization

Inventors: Anita Chowdhry (Saratoga, CA); Subir Ghosh (San Jose, CA)
Assignee: nComputing Inc.
G09G5/14G09G5/393G09G5/395G09G5/397G09G2340/02G09G2340/0407G09G2350/00G09G2360/18G09G2370/022
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Quick Facts
Patent No.
US 8,907,987
App. No.
12/908,365
Granted
Dec 9, 2014
Kind
B2
Abstract

The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, full-motion video may also be displayed in a window defined in the frame buffer. If the native resolution of the full-motion video is larger than the window defined in said frame buffer then valuable memory space and memory bandwidth is being wasted by writing said larger full-motion video in a memory system (and later reading it back) when some data from the full-motion video will be discarded. Thus, a video pre-processor is disclosed to reduce the size of the full-motion video before that full-motion video is written into a memory system. The video pre-processor will scale the full-motion video down to a size no larger than the window defined in the frame buffer.

Claims (52)

1. A digital video display system, said digital video display system comprising:

a frame buffer, said frame buffer to store a pixel representation of a display screen;

a full-motion video window definition, said full-motion video window definition to define an area of said frame buffer wherein a full-motion video is to be displayed;

a full-motion video buffer, said full-motion video buffer to store only said full-motion video to be displayed in a display area defined by said full-motion video window definition, said frame buffer and said full-motion video buffer both residing in shared memory; and

a video pre-processor, said video pre-processor configured to:

compare a native resolution of decoded full-motion video information received to said area defined by said full-motion video window definition;

in response to a determination that said native resolution is larger than said area defined by said full-motion video window definition:

scale down said decoded full-motion video information received to a size no larger than said full-motion video window definition by scaling down said decoded full-motion video information horizontally and vertically before writing a scaled-down digital representation in said full-motion video buffer, wherein luminance data of said decoded full-motion video information is scaled down separately from chrominance data of said decoded full-motion video information and wherein said chrominance data is scaled down based on a sampling ratio between said luminance data and said chrominance data; and

write said scaled-down digital representation of said full-motion video in said full-motion video buffer; and

in response to a determination that said native resolution is smaller than said area defined by said full-motion video window definition, write a digital representation of said full-motion video in said full-motion video buffer without first upscaling said full-motion video.

2. The digital video display system as set forth in claim 1 , said digital video display system further comprising:

a digital video decoder, said digital video decoder to provide said decoded full-motion video information to said video pre-processor.

3. The digital video display system as set forth in claim 2 , further comprising:

a pre-processing module comprising said video pre-processor and said digital video decoder, wherein said providing said decoded full-motion video and said scaling down said decoded full-motion video information are performed without accessing a memory external to said pre-processing module.

4. The digital video display system as set forth in claim 3 , wherein said video pre-processor is further configured to rasterize said scaled-down digital representation without accessing said memory external to said pre-processing module.

5. The digital video display system as set forth in claim 2 , wherein said digital video decoder provides said decoded full-motion video information in a macro block format.

6. The digital video display system as set forth in claim 1 wherein said video pre-processor includes:

a data output system, said data output system to write data to said shared memory system in multi-cycle bursts.

7. The digital video display system as set forth in claim 1 wherein said video pre-processor comprises:

a horizontal resizing logic block to resize said full-motion video in a horizontal direction;

a vertical resizing logic block to resize said full-motion video in a vertical direction; and

a memory buffer residing between said horizontal resizing logic block and said vertical resizing logic block.

8. The digital video display system as set forth in claim 1 , said digital video display system further comprising:

a video output system, said video output system to read from said frame buffer and from said full-motion video buffer to generate a video output signal.

9. The digital video display system as set forth in claim 8 wherein said video output system comprises an on-the-fly Key color generation system that only reads data from said frame buffer or said full-motion video buffer for each portion of the display screen.

10. The digital video display system as set forth in claim 9 wherein said video pre-processor receives said full-motion video window definition from said on-the-fly Key color generation system.

11. The digital video display system as set forth in claim 1 wherein said video pre-processor outputs said scaled-down digital representation of said full-motion video in a rasterized format.

12. The digital video display system as set forth in claim 1 wherein said video pre-processor is combined with a full-motion video decoder.

13. A method of processing display information within digital video display system, said method comprising:

writing desktop display data in a frame buffer, said frame buffer comprising a pixel representation of a desktop display to be output on a display screen, said pixel representation of said desktop display including a full-motion video window area wherein a full-motion video is to be displayed defined by a full-motion video window definition;

comparing a native resolution of decoded full-motion video information received to said area defined by said full-motion video window definition;

in response to a determination that said native resolution is larger than said area defined by said full-motion video window definition:

processing said decoded full-motion video stream with a video pre-processor, said video pre-processor scaling down said decoded full-motion video stream horizontally and vertically to a size no larger than said full-motion video window area wherein said full-motion video is to be displayed, wherein luminance data of said decoded full-motion video stream is scaled down separately from chrominance data of said decoded full-motion video stream and wherein said chrominance data is scaled down based on a sampling ratio between said luminance data and said chrominance data; and

after said processing of said decoded full-motion video stream, writing a scaled down digital representation of said full-motion video into a full-motion video buffer storing only said full-motion video to be displayed, said frame buffer and said full-motion video buffer both residing in shared memory; and

in response to a determination that said native resolution is smaller than said area defined by said full-motion video window definition, writing a digital representation of said full-motion video in said full-motion video buffer without first upscaling said full-motion video.

14. The method of processing display information as set forth in claim 13 , said method further comprising:

decoding encoded digital video with a digital video decoder, said digital video decoder providing said decoded full-motion video information to said video pre-processor.

15. The method of processing display information as set forth in claim 14 , wherein said video pre-processor and said digital video decoder are included in a pre-processing module and wherein decoding said encoded digital video and processing said decoded full-motion video stream are performed without accessing a memory external to said pre-processing module.

16. The method of processing display information as set forth in claim 15 , further comprising:

rasterizing said scaled-down digital representation without accessing said memory external to said pre-processing module.

17. The method of processing display information as set forth in claim 14 , wherein said digital video decoder provides said decoded full-motion video information in a macro block format.

18. The method of processing display information as set forth in claim 13 wherein said writing said scaled down digital representation of said full-motion video into said full-motion video buffer comprises writing data to said shared memory system in multi-cycle bursts.

19. The method of processing display information as set forth in claim 13 wherein processing a decoded full-motion video stream comprises:

resizing said full-motion video in a horizontal direction; and

resizing said full-motion video in a vertical direction.

20. The method of processing display information as set forth in claim 13 , said method further comprising:

reading from said frame buffer and from said full-motion video buffer with a video output system to generate a video output signal.

21. The method of processing display information as set forth in claim 20 wherein said video output system comprises an on-the-fly Key color generation system that only reads data from said frame buffer or said full-motion video buffer for each portion of the display screen.

22. The method of processing display information as set forth in claim 20 wherein said video pre-processor receives said full-motion video window definition from said on-the-fly Key color generation system.

23. The method of processing display information as set forth in claim 13 wherein said video pre-processor outputs said scaled-down digital representation of said full-motion video in a rasterized format.

24. The method of processing display information as set forth in claim 13 , said method further comprising:

decoding an encoded full-motion video stream with a full-motion video decoder to produce said decoded full-motion video stream.

Assignments (11)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2019
From: NCOMPUTING, INC.
To: NCOMPUTING DE, LLC
Reel/Frame 048031/0929 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2017
From: NCOMPUTING DE, LLC
To: NCOMPUTING GLOBAL, INC.
Reel/Frame 043237/0074 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ADDRESS OF ASSIGNEE PREVIOUSLY RECORDED AT REEL: 030390 FRAME: 0535. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 6, 2015
From: NCOMPUTING, INC.
To: ARES CAPITAL CORPORATION
Reel/Frame 037058/0390 →
SECURITY AGREEMENT Recorded Feb 6, 2014
From: NCOMPUTING, INC., A DELAWARE CORPORATION; NCOMPUTING, INC., A CALIFORNIA CORPORATION
To: PINNACLE VENTURES, L.L.C.
Reel/Frame 032166/0456 →
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT APPLICATION NUMBER 12/908,362 PREVIOUSLY RECORDED ON REEL 025473 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT PATENT APPLICATION NUMBER SHOULD HAVE BEEN 12/908,365 AS INDICATED IN THE AGREEMENT. Recorded Dec 4, 2013
From: NCOMPUTING, INC.
To: SAND HILL CAPITAL IV, LP
Reel/Frame 031788/0734 →
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT APPLICATION NUMBER 12/908,362 PREVIOUSLY RECORDED ON REEL 031635 FRAME 0651. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT PATENT APPLICATION NUMBER SHOULD HAVE BEEN 12/908,365. Recorded Dec 4, 2013
From: NCOMPUTING, INC.
To: SAND HILL CAPITAL IV, LP
Reel/Frame 031765/0487 →
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT APPLICATION NUMBER 12/908,362 ERRONEOUSLY RECORDED AGAINST PREVIOUSLY RECORDED ON REEL 025473 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE THE CORRECT PATENT APPLICATION NUMBER SHOULD HAVE BEEN 12/908,365 AS INDICATED IN THE AGREEMENT. Recorded Nov 13, 2013
From: NCOMPUTING, INC.
To: SAND HILL CAPITAL IV, LP
Reel/Frame 031635/0651 →
SECURITY AGREEMENT Recorded May 9, 2013
From: NCOMPUTING, INC.
To: ARES CAPITAL CORPORATION
Reel/Frame 030390/0535 →
RELEASE OF SECURITY INTEREST Recorded Mar 20, 2013
From: SAND HILL CAPITAL IV, LP
To: NCOMPUTING, INC.
Reel/Frame 030052/0816 →
SECURITY AGREEMENT Recorded Dec 11, 2010
From: NCOMPUTING, INC.
To: SAND HILL CAPITAL IV, L.P.
Reel/Frame 025473/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2010
From: CHOWDHRY, ANITA; GHOSH, SUBIR
To: NCOMPUTING INC.
Reel/Frame 025167/0294 →
Continuity (1)
Related Publication 20120098864A1 · Apr 26, 2012