Organic thin film transistor array panel and manufacturing method thereof
View Patent ↗An organic thin film transistor array panel according to an embodiment of the present invention includes: a substrate; a data line disposed on the substrate; an insulating layer disposed on the data line and having a contact hole exposing the data line; a first electrode disposed on the insulating layer and connected to the data line through the contact hole; a second electrode disposed on the insulating layer; an organic semiconductor disposed on the first and the second electrodes; a gate insulator disposed on the organic semiconductor; and a gate electrode disposed on the gate insulator.
1. A method of manufacturing an organic thin film transistor array panel, the method comprising:
forming a data line;
forming a first insulating layer on the data line;
forming a contact hole in the first insulating layer to expose portions of the data line;
forming a source electrode electrically connected to the data line through the contact hole;
forming a pixel electrode including a drain electrode;
forming, a second insulating layer having a first opening exposing a portion of the source electrode and a portion of the drain electrode;
placing a semiconductor in the first opening;
forming an island-shaped gate insulator over the semiconductor in the first opening, the island-shaped gate insulator having an outer boundary defined by the first opening which contains the semiconductor; and
forming a gate electrode on the gate insulator.
2. The method of claim 1 , wherein placing the semiconductor in the first opening is performed by inkjet printing.
3. The method of claim 2 , wherein placing the semiconductor in the first opening comprises:
printing into the first opening, a semiconductor material dissolved in a solvent; and
removing the solvent.
4. The method of claim 2 , wherein forming the gate insulator comprises inkjet printing.
5. The method of claim 1 , wherein the second insulating layer includes a second opening exposing a portion of the pixel electrode.
6. The method of claim 1 , wherein forming the source electrode and the pixel electrode comprises:
depositing an indium tin oxide layer at a room temperature; and
patterning the indium tin oxide layer by lithography and etch.
7. The method of claim 6 , wherein patterning the indium tin oxide layer comprises using an etchant containing an alkaline ingredient.
8. The method of claim 1 , wherein forming the first insulating layer comprises:
forming a silicon nitride film; and
forming an organic film on the silicon nitride film.
9. The method of claim 1 , further comprising forming a passivation member on the gate electrode.
10. The method of claim 1 , wherein the semiconductor comprises an organic semiconductor.