Method for controlling critical dimension in semiconductor production process, and semiconductor manufacturing line supporting the same
View Patent ↗A critical dimension controlling method in a semiconductor production process includes determining whether a model is to undergo a discontinuous production process when a run is inserted in a semiconductor manufacturing line, applying an offset for said model or a common offset for a model group including said model according to the determination, executing a production process in dependence upon a process variation along with the offset for the model or the common offset for the model group, and measuring an actual critical dimension in the production process. The offset for the model is calculated based on a previously measured actual critical dimension, and the calculated offset for the model is applied to the calculation of the common offset for the model group.
1. A critical dimension controlling method in a semiconductor production process, comprising:
determining whether a model is to undergo a discontinuous production process when a run is inserted in a semiconductor manufacturing line;
applying an offset for said model or a common offset for a model group including said model according to the determination;
executing a production process in dependence upon a process variation along with the offset for the model or the common offset for the model group; and
measuring an actual critical dimension in the production process,
the offset for the model is calculated based on a previously measured actual critical dimension, and the calculated offset for the model is applied to the calculation of the common offset for the model group.
2. The critical dimension controlling method of claim 1 , wherein the common offset is calculated by a difference between the calculated offset for the model and a model offset deviation.
3. The critical dimension controlling method of claim 2 , wherein the model offset deviation is calculated by a difference between an offset of a reference model in the model group and the offset for said model.
4. The critical dimension controlling method of claim 3 , further comprising calculating an offset for the discontinuous production process in dependence upon the common offset and the model offset deviation.
5. The critical dimension controlling method of claim 4 , wherein the offset for the discontinuous production process is calculated as the sum of the common offset and the model offset deviation.
6. The critical dimension controlling method of claim 1 , wherein the model group is a group of models producing a same layer or a same element having a same target critical dimension in the discontinuous production process.
7. The critical dimension controlling method of claim 1 , wherein the determination of whether the model is to undergo the discontinuous production process is performed with reference to a time interval between the insertion of the run and an insertion of a previous run.
8. The critical dimension controlling method of claim 1 , further comprising storing the measured actual critical dimension and the calculated offset for the model in a memory.
9. The critical dimension controlling method of claim 1 , wherein the process variation is calculated in dependence upon the calculated offset for the model and a target critical dimension.
10. A semiconductor manufacturing line, comprising:
a process tool executing a semiconductor production process;
a measuring tool obtaining measurement data in a process result of semiconductor production process; and
a controller controlling the process tool and the measuring tool,
the controller determines whether a model is to undergo a discontinuous production process when a run is inserted in a semiconductor manufacturing line, and applies an offset for the model or a common offset for a model group including said model, according to the determination,
to the offset for the model is calculated based on a previously obtained measurement data, and the calculated offset for the model is applied to the calculation of the common offset for the model group.
11. The semiconductor manufacturing line of claim 10 , wherein the controller calculates the common offset by a difference between the calculated offset for the model and a model offset deviation.
12. The semiconductor manufacturing line of claim 11 , wherein the controller calculates the model offset deviation by a difference between an offset of a reference model in the model group and the offset for said model.
13. The semiconductor manufacturing line of claim 12 , wherein the controller calculates an offset for the discontinuous production process as the sum of the common offset and the model offset deviation.
14. The semiconductor manufacturing line of claim 10 , wherein the controller determines whether the model is to undergo the discontinuous production process with reference to a time interval between the insertion of the run and an insertion of a previous run.
15. The semiconductor manufacturing line of claim 10 , wherein
the controller calculates a process variation satisfying a target critical dimension in dependence upon the calculated offset for the model and the target critical dimension, and
the process tool executes the semiconductor production process in dependence upon the process variation.
16. The semiconductor manufacturing line of claim 10 , further comprising a memory storing the measurement data and the calculated offset for the model.