IP Library Granted Patent US 8,587,322
Granted Patent B2
US 8,587,322 · App. 12/913,196 · Granted Nov 19, 2013

Methods and apparatus for motor emulation

Inventor: William A. Peterson (Vestal, NY)
Assignee: E & M Power, Inc.
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Quick Facts
Patent No.
US 8,587,322
App. No.
12/913,196
Granted
Nov 19, 2013
Kind
B2
Abstract

Methods and apparatus provide for: a first DC bus operating to support a first DC voltage potential and for connecting to a DC input of a motor driver inverter circuit; a motor emulator circuit operating to emulate a polyphase motor and including polyphase output terminals for connecting to a polyphase output of the motor driver inverter circuit; a second DC bus operating to support a second DC voltage potential to a DC input of the motor emulator circuit; and a bi-directional DC-DC power supply coupled between the first and second DC busses, and operating to both: (i) add voltage potential to the first DC voltage potential to produce the higher, second DC voltage potential on the second DC bus, and (ii) subtract voltage potential from the second DC voltage potential to produce the lower, first DC voltage potential on the first DC bus.

Claims (56)

1. An apparatus, comprising:

a first DC bus operating to support a first DC voltage potential and for connecting to a DC input of a motor driver inverter circuit;

a motor emulator circuit operating to emulate a polyphase motor and including polyphase output terminals for connecting to a polyphase output of the motor driver inverter circuit;

a second DC bus operating to support a second DC voltage potential to a DC input of the motor emulator circuit; and

a bi-directional DC-DC power supply coupled between the first and second DC busses, and operating to both: (i) add voltage potential to the first DC voltage potential to produce the higher, second DC voltage potential on the second DC bus, and (ii) subtract voltage potential from the second DC voltage potential to produce the lower, first DC voltage potential on the first DC bus.

2. The apparatus of claim 1 , wherein at least one of:

the bi-directional DC-DC power supply is rated at a fraction of a power rating of the motor emulator circuit;

the bi-directional DC-DC power supply is rated at less than about 50% of the power rating of the motor emulator circuit; and

the bi-directional DC-DC power supply is rated at about 10% or less of the power rating of the motor emulator circuit.

3. The apparatus of claim 1 , wherein:

the bi-directional DC-DC power supply operates to add the voltage potential (ΔV) to the first DC voltage potential (V 1 ) to the second DC voltage potential; and

the bi-directional DC-DC power supply is rated at about 100×(ΔV/V 1 ) percent of a power rating of the motor emulator circuit.

4. The apparatus of claim 1 , wherein:

the first DC bus includes a positive node (+V 1 ) and a negative node (−V 1 ), each with reference to a reference potential, and each of nodes +V 1 and −V 1 exhibiting the same magnitude;

the second DC bus includes a positive node (+V 2 ) and a negative node (−V 2 ), each with reference to the reference potential, and each of nodes +V 2 and −V 2 exhibiting the same voltage magnitude;

the bi-directional DC-DC power supply adds a positive voltage potential (+ΔV/2) to the positive node +V 1 to produce the voltage on the positive node +V 2 ; and

the bi-directional DC-DC power supply adds a negative voltage potential (−ΔV/2) to the negative node −V 1 to produce the voltage on the negative node −V 2 .

5. The apparatus of claim 4 , wherein the bi-directional DC-DC power supply is rated at 100×(+ΔV/2−(−ΔV/2))/(+V 2 −(−V 2 )) percent of a power rating of the motor emulator circuit.

6. The apparatus of claim 4 , wherein the bi-directional DC-DC power supply includes a DC autotransformer circuit to produce +V 1 , −V 1 , +ΔV/2, −ΔV/2, −V 2 , and +V 2 .

7. The apparatus of claim 6 , wherein the DC autotransformer circuit includes:

a transformer including a primary winding of M×N turns, a first secondary winding of N turns, and a second secondary winding of N turns, where N and M×N are integers;

a primary switching transistor circuit operating to couple the primary winding of the transformer to the positive and negative nodes of the first DC bus;

a first, secondary switching transistor circuit operating to couple the first secondary winding of the transformer to the positive node of the first DC bus and to the positive node of the second DC bus;

a second, secondary switching transistor circuit operating to couple the second secondary winding of the transformer to the negative node of the first DC bus and to the negative node of the second DC bus; and

a controller operating to open and close transistor switches within the primary, first secondary, and second secondary switching circuits in order to produce +V 1 , −V 1 , +ΔV, −ΔV, −V 2 , and +V 2 .

8. The apparatus of claim 1 , further comprising a DC power supply coupled between a main source of power and one of:

the first DC bus, where the DC power supply operates to produce voltage at the first DC voltage potential and provide power to offset power conversion losses in the motor driver inverter circuit, the motor emulator circuit, and the bi-directional DC-DC power supply; and

the second DC bus, where the DC power supply operates to produce voltage at the second DC voltage potential and provide power to offset power conversion losses in the motor driver inverter circuit, the motor emulator circuit, and the bi-directional DC-DC power supply.

9. The apparatus of claim 8 , wherein the DC power supply is a uni-directional DC power supply operating only to source power.

10. The apparatus of claim 8 , wherein at least one of:

the DC power supply is rated at a fraction of a power rating of the motor emulator circuit;

the DC power supply is rated at less than about 50% of the power rating of the motor emulator circuit; and

the DC power supply is rated at about 10% or less of the power rating of the motor emulator circuit.

11. The apparatus of claim 1 , further comprising:

a differential mode inductor, including first, second and third windings wound in a differential mode configuration; and

a common mode inductor, including first, second and third windings wound in a common mode configuration, wherein:

the respective first, second, and third windings of the differential mode inductor are coupled in series with the first, second, and third windings of the common mode inductor, and

the respective pairs of series coupled windings of the differential mode inductor and the common mode inductor are coupled between the respective polyphase terminals of the motor emulator circuit and the motor driver inverter circuit.

12. The apparatus of claim 11 , further comprising:

a capacitor network coupled in a Y configuration from the respective junctions of the respective pairs of series coupled windings of the differential mode inductor and the common mode inductor,

wherein a voltage at a common node of the capacitor network is an emulation of a Z-axis voltage, which is a common mode voltage, of the motor driver inverter circuit.

13. The apparatus of claim 12 , wherein the motor emulator circuit operates to commutate internal switching transistors thereof based on the emulated Z-axis voltage.

14. A method, comprising:

emulating a polyphase motor using an emulation inverter circuit operating under the control of a pulse width modulation circuit, the emulation inverter circuit including: (i) polyphase output terminals for connecting to a polyphase output of a motor driver inverter circuit, and (ii) a DC input;

subtracting a voltage potential (ΔV) from the DC input of the emulation inverter circuit to produce a DC input for the motor driver inverter circuit; and

adding the voltage potential (ΔV) to the DC input of the motor driver inverter circuit to produce the DC input for the emulation inverter circuit.

15. The method of claim 14 , wherein:

the DC input of the motor driver inverter circuit includes a positive node (+V 1 ) and a negative node (−V 1 ), each with reference to a reference potential, and each of nodes +V 1 and −V 1 exhibiting the same magnitude; and

the DC input of the emulation inverter circuit includes a positive node (+V 2 ) and a negative node (−V 2 ), each with reference to the reference potential, and each of nodes +V 2 and −V 2 exhibiting the same voltage magnitude.

16. The method of claim 15 , further comprising:

adding a positive voltage potential (+ΔV) to the positive node +V 1 to produce the voltage on the positive node +V 2 ; and

adding a negative voltage potential (−ΔV) to the negative node −V 1 to produce the voltage on the negative node −V 2 .

17. The method of claim 15 , further comprising:

adding a negative voltage potential (−ΔV) to the positive node +V 2 to produce the voltage on the positive node +V 1 ; and

adding a positive voltage potential (+ΔV) to the negative node −V 2 to produce the voltage on the negative node −V 1 .

18. The method of claim 14 , further comprising offsetting power conversion losses in at least the motor driver inverter circuit and the emulator inverter circuit using a DC power supply coupled from a main source of power to the DC input of the motor driver inverter circuit.

Assignments (4)
SECURITY INTEREST Recorded Aug 19, 2026
From: D&V ELECTRONICS LTD.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 075713/0730 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2019
From: MOTORCAR PARTS OF AMERICA, INC.
To: D&V ELECTRONICS LTD.
Reel/Frame 048373/0042 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2019
From: MECHANICAL POWER CONVERSION LLC
To: MOTORCAR PARTS OF AMERICA, INC.
Reel/Frame 048253/0790 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2010
From: PETERSON, WILLIAM A.
To: E&M POWER, INC.
Reel/Frame 025203/0661 →
Continuity (1)
Related Publication 20120105072A1 · May 3, 2012