Analog-to-digital converter on two bits with successive approximations
View Patent ↗The analog-to-digital converter comprises a first stage in which a voltage to be converted is applied to the input of a first comparator. The first comparator delivers a first digital result representative of the comparison between the voltage to be converted and the reference voltage on a first digital output. The first digital output is connected to means for calculating a first intermediate voltage. A second comparator compares the first intermediate voltage with the reference voltage and delivers a second digital result on a second digital output terminal. The digital output terminal is connected to second means for calculating a residual voltage according to the voltage to be converted, the first and second voltages and the first and second digital results.
1. A successive-approximation analog-to-digital converter for converting an input voltage on at least two bits comprising:
a first circuitry configured for setting an upper limit voltage and a lower limit voltage of a conversion range, the input voltage being comprised in the conversion range,
an input terminal receiving the input voltage,
a first comparator performing a first comparison of the input voltage with a first reference voltage and delivering a first digital bit according to the first comparison,
a first calculator comprising a first analog input connected to the input terminal, second and third inputs connected to the first circuitry so as to receive the upper limit voltage and the lower limit voltage, a fourth input connected to the first comparator so as to receive the first digital bit and an output providing an intermediate analog voltage,
a second comparator performing a second comparison of the intermediate analog voltage with a second reference voltage and delivering a second digital bit according to the second comparison,
a second calculator comprising a first analog input connected to the input terminal, second and third inputs connected to the first circuitry so as to receive the upper limit voltage and the lower limit voltage, a fourth input connected to the first single-bit comparator so as to receive the first digital bit, a fifth input connected to the second comparator so as to receive the second digital bit and an output providing an residual analog voltage.
2. Converter according to claim 1 , wherein the first comparator is a single-bit comparator delivering one bit according to a position of the input voltage with a reference voltage located at an equipotential of the lower and upper limit voltages.
3. Converter according to claim 1 , wherein the second comparator is a single-bit comparator.
4. Converter according to claim 3 , wherein the second calculator is configured so as to deliver the residual analog voltage according to 4Vin−(Va+Vb)+Bi.(Va−Vb)+ B i.(Vb−Va)−(Va+Vb)/2+B i+1 .(Va−Vb)/2+ B i+1 .(Vb−Va) and wherein
Vin is the input voltage
Va is the lower limit voltage
Vb is the higher limit voltage,
B i is the complementary value of the first bit, B i+1 is the complementary value of the second bit.
5. Converter according to claim 1 , wherein the first comparator comprises two single-bit comparators configured so as to divide the conversion range into three elementary ranges, the first comparator delivers two elementary bits according to the location of the input voltage in the three elementary ranges and wherein the first calculator and the second calculator comprise an additional input connected to the first comparator, the first calculator and the second calculators receiving the first and second elementary bits.
6. Converter according to claim 1 , wherein the second comparator comprises two single-bit comparators configured so as to divide the conversion range into three elementary ranges, the second comparator delivers two elementary bits according to the location of the input voltage in the three elementary ranges and wherein the second calculator comprises an additional input connected to the second comparator, the second calculators receiving the first and second elementary bits.
7. Converter according to claim 6 , wherein the second calculator is configured so as to deliver the residual analog voltage according to 4Vin−2(Bi − AND Bi + ).Vref+−2(Bi − OR Bi + ).(Va+Vb)/2−2( Bi − AND Bi + ).Vref−—(B i+1 − AND B i+1 + ). Vref+−(B i+1 − OR B i+1 + ).(Va+Vb)/2−( B i+1 − AND B i+1 + ).Vref−. and wherein Vin is the input voltage, Va is the lower limit voltage, Vb is the higher limit voltage, Vref+ is an upper reference voltage, Vref− is a lower reference voltage, B i is the complementary value of the first bit, B i+1 is the complementary value of the second bit.
8. Converter according to claim 1 , wherein the output of the second calculator is electrically coupled to the input terminal.