IP Library Granted Patent US 8,593,824
Granted Patent B2
US 8,593,824 · App. 12/913,394 · Granted Nov 26, 2013

Tamper secure circuitry especially for point of sale terminal

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Quick Facts
Patent No.
US 8,593,824
App. No.
12/913,394
Granted
Nov 26, 2013
Kind
B2
Abstract

Tamper secure circuitry including a first printed circuit board having mounted thereon circuit components and a slotted anti-tamper grid containing printed circuit board mounted onto the first printed circuit board defining at least one slot and arranged to overlie at least some of the circuit components, which are located in a volume defined by the at least one slot and the first printed circuit board.

Claims (33)

1. Tamper secure circuitry comprising:

a first printed circuit board having mounted thereon circuit components; and

a slotted anti-tamper grid containing printed circuit board mounted onto said first printed circuit board defining at least one slot and arranged to overlie at least some of said circuit components, which are located in a volume defined by said at least one slot and said first printed circuit board,

said first printed circuit board being a multilayer printed circuit board and including tamper sensitive vias which directly underlie the bounds of said volume,

said tamper sensitive vias being through hole vias.

2. Tamper secure circuitry according to claim 1 and wherein said circuit components mounted onto said first printed circuit board underlying said slotted anti-tamper grid containing printed circuit board include tamper sensitive circuit components.

3. Tamper secure circuitry according to claim 2 and wherein at least some of said circuit components which are located in said volume overlie at least some of said tamper sensitive vias which underlie said volume.

4. Tamper secure circuitry according to claim 3 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said tamper sensitive vias are tamper sensitive components.

5. Tamper secure circuitry according to claim 4 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said tamper sensitive vias are not tamper sensitive components.

6. Tamper secure circuitry according to claim 1 and wherein at least some of said circuit components which are located in said volume overlie at least some of said tamper sensitive vias which underlie said volume.

7. Tamper secure circuitry according to claim 6 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said tamper sensitive vias are tamper sensitive components.

8. Tamper secure circuitry according to claim 7 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said tamper sensitive vias are not tamper sensitive components.

9. Tamper secure circuitry according to claim 1 and wherein said circuit components mounted onto said first printed circuit board underlying said slotted anti-tamper grid containing printed circuit board include data security critical circuit components.

10. Tamper secure circuitry according to claim 9 and wherein said first printed circuit board also includes data security critical vias which underlie said volume.

11. Tamper secure circuitry according to claim 10 and wherein at least some of said circuit components which are located in said volume overlie at least some of said data security critical vias which underlie said volume.

12. Tamper secure circuitry according to claim 11 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said data security critical vias are tamper sensitive components.

13. Tamper secure circuitry according to claim 11 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said data security critical vias are not tamper sensitive components.

14. Tamper secure circuitry according to claim 1 and wherein said first printed circuit board also includes data security critical vias which underlie said volume.

15. Tamper secure circuitry according to claim 14 and wherein at least some of said circuit components which are located in said volume overlie at least some of said data security critical vias which underlie said volume.

16. Tamper secure circuitry according to claim 15 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said data security critical vias are tamper sensitive components.

17. Tamper secure circuitry according to claim 15 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said data security critical vias are not tamper sensitive components.

18. Tamper secure circuitry according to claim 1 and wherein said circuit components mounted onto said first printed circuit board underlying said slotted anti-tamper grid containing printed circuit board include tamper sensitive and data security critical circuit components.

19. Tamper secure circuitry according to claim 18 and wherein said first printed circuit board also includes data security critical vias which underlie said volume.

20. Tamper secure circuitry according to claim 19 and wherein at least some of said circuit components which are located in said volume overlie at least some of said tamper sensitive and data security critical vias which underlie said volume.

21. Tamper secure circuitry according to claim 20 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said tamper sensitive and data security critical vias are tamper sensitive components.

22. Tamper secure circuitry according to claim 20 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said data security critical vias are not tamper sensitive components.

23. Tamper secure circuitry according to claim 1 and wherein said first printed circuit board also includes data security critical vias which underlie said volume.

24. Tamper secure circuitry according to claim 23 and wherein at least some of said circuit components which are located in said volume overlie at least some of said tamper sensitive and data security critical vias which underlie said volume.

25. Tamper secure circuitry according to claim 24 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said data security critical vias are tamper sensitive components.

26. Tamper secure circuitry according to claim 24 and wherein at least some of said circuit components which are located in said volume and overlie at least some of said data security critical vias are not tamper sensitive components.

27. Tamper secure circuitry according to claim 1 and also including a secured integrated circuit underlying a portion of said first printed circuit board which underlies said volume.

28. Tamper secure circuitry according to claim 27 and wherein said through hole vias are connected to said secured integrated circuit underlying a portion of said first printed circuit board which underlies said volume.

29. Tamper secure circuitry according to claim 1 and wherein said secured integrated circuit is a tamper sensitive integrated circuit.

Assignments (8)
ASSIGNMENT OF SECURITY INTEREST IN PATENT COLLATERAL RECORDED AT R/F 046920-0784 Recorded Apr 28, 2025
From: UBS AG, STAMFORD BRANCH, AS SUCCESSOR TO CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS ASSIGNOR
To: BARCLAYS BANK PLC, AS ASSIGNEE
Reel/Frame 071095/0667 →
AFFIDAVIT TO AFFIRM THE RELEASE OF SECURITY INTEREST IN PATENTS AND TRADEMARKS EFFECTIVE AUGUST 20, 2018 Recorded Apr 14, 2025
From: JPMORGAN CHASE BANK, N.A.
To: VERIFONE, INC.
Reel/Frame 072942/0674 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 46920/0817 Recorded May 10, 2019
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: VERIFONE SYSTEMS, INC.; VERIFONE, INC.; HYPERCOM CORPORATION
Reel/Frame 049150/0190 →
SECOND LIEN PATENT SECURITY AGREEMENT Recorded Aug 23, 2018
From: VERIFONE, INC.; HYPERCOM CORPORATION
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH AS COLLATERAL AGENT
Reel/Frame 046920/0817 →
FIRST LIEN PATENT SECURITY AGREEMENT Recorded Aug 23, 2018
From: VERIFONE, INC.; HYPERCOM CORPORATION
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH AS COLLATERAL AGENT
Reel/Frame 046920/0784 →
RELEASE (R033282F0757) Recorded Aug 21, 2018
From: JPMORGAN CHASE BANK, N.A.
To: VERIFONE, INC.; HYPERCOM CORPORATION; GLOBAL BAY MOBILE TECHNOLOGIES, INC.
Reel/Frame 046864/0909 →
CHANGE OF ADDRESS Recorded May 30, 2016
From: VERIFONE, INC.
To: VERIFONE, INC.
Reel/Frame 038845/0718 →
SECURITY INTEREST Recorded Jul 9, 2014
From: VERIFONE, INC.; HYPERCOM CORPORATION; GLOBAL BAY MOBILE TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 033282/0757 →