Method, system, and apparatus for RF and DC switching
View Patent ↗Embodiments of RF and DC switching are described generally herein. Other embodiments may be described and claimed.
1. An apparatus for generating a second signal from a first signal based on a bias signal, including:
a first summing module for summing the bias signal to the first signal to generate a first bias signal;
a second summing module for summing the bias signal to the second signal to generate a second bias signal; and
a controllable signal processing module, the module receiving the first signal, the first bias signal, and the second bias signal and generating the second signal from the first signal based the combination of the first bias signal and the second bias signal, the controllable signal processing module including a capacitive effect.
2. The apparatus for generating a second signal from a first signal based on a bias signal of claim 1 , further including a first amplifier for amplifying the first bias signal and the controllable signal processing module receiving the first signal, the amplified first bias signal, and the second bias signal and generating the second signal from the first signal based the combination of the amplified first bias signal and the second bias signal.
3. The apparatus for generating a second signal from a first signal based on a bias signal of claim 2 , further including a second amplifier for amplifying the second bias signal and the controllable signal processing module receiving the first signal, the amplified first bias signal, and the amplified second bias signal and generating the second signal from the first signal based the combination of the amplified first bias signal and the amplified second bias signal.
4. The apparatus for generating a second signal from a first signal based on a bias signal of claim 1 , the controllable signal processing module including a CMOS transistor, the transistor including a gate, source, and a drain and the combination of the first bias signal and the second bias signal received at the gate, the first signal received on the source, and the second signal generated on the drain.
5. The apparatus for generating a second signal from a first signal based on a bias signal of claim 1 , the first signal including an RF component.
6. The apparatus for generating a second signal from a first signal based on a bias signal of claim 5 , the first signal further including a baseband component.
7. The apparatus for generating a second signal from a first signal based on a bias signal of claim 5 , the first signal further including a DC component.
8. The apparatus for generating a second signal from a first signal based on a bias signal of claim 1 , the controllable signal processing module including a plurality of CMOS transistors, each transistor including a gate, source, and a drain and the combination of the first bias signal and the second bias signal received at the gate of each transistor.
9. The apparatus for generating a second signal from a first signal based on a bias signal of claim 1 , the controllable signal processing module including a plurality of CMOS transistors, each transistor including a gate, source, and a drain and the combination of the first bias signal and the second bias signal approximately equally received at the gate of each transistor.
10. The apparatus for generating a second signal from a first signal based on a bias signal of claim 3 , wherein the apparatus is an RF switch and the controllable signal processing modulates the first signal to generate the second signal based on the combination of the amplified first bias signal and the amplified second bias signal.
11. The apparatus for generating a second signal from a first signal based on a bias signal of claim 1 , the controllable signal processing module including a plurality of CMOS transistors and a plurality of resistors, each transistor including a gate, source, and a drain and the combination of the first bias signal and the second bias signal received at the gate of each transistor via at least one resistor.
12. The apparatus for generating a second signal from a first signal based on a bias signal of claim 1 , the controllable signal processing module including a plurality of CMOS transistors and a plurality of resistors, each transistor including a gate, source, and a drain and the combination of the first bias signal and the second bias signal approximately equally received at the gate of each transistor via at least one resistor.
13. An method for generating a second signal from a first signal based on a bias signal, including:
summing the bias signal to the first signal to generate a first bias signal;
summing the bias signal to the second signal to generate a second bias signal; and
at a controllable signal processing module receiving the first signal, the first bias signal, and the second bias signal and generating the second signal from the first signal based the combination of the first bias signal and the second bias signal, the controllable signal processing module including a capacitive effect.
14. The method for generating a second signal from a first signal based on a bias signal of claim 13 , further including amplifying the first bias signal and at controllable signal processing module receiving the first signal, the amplified first bias signal, and the second bias signal and generating the second signal from the first signal based the combination of the amplified first bias signal and the second bias signal.
15. The method for generating a second signal from a first signal based on a bias signal of claim 14 , further amplifying the second bias signal and at the controllable signal processing module receiving the first signal, the amplified first bias signal, and the amplified second bias signal and generating the second signal from the first signal based the combination of the amplified first bias signal and the amplified second bias signal.
16. The method for generating a second signal from a first signal based on a bias signal of claim 13 , wherein the controllable signal processing module includes a CMOS transistor, the transistor including a gate, source, and a drain and receiving the combination of the first bias signal and the second bias signal at the gate, the first signal received on the source, and the second signal generated on the drain.
17. The method for generating a second signal from a first signal based on a bias signal of claim 13 , the first signal including an RF component.
18. The method for generating a second signal from a first signal based on a bias signal of claim 17 , the first signal further including a baseband component.
19. The method for generating a second signal from a first signal based on a bias signal of claim 17 , the first signal further including a DC component.
20. The method for generating a second signal from a first signal based on a bias signal of claim 13 , the controllable signal processing including a plurality of CMOS transistors, each transistor including a gate, source, and a drain and receiving the combination of the first bias signal and the second bias signal at the gate of each transistor.