Semiconductor storage device and method of manufacturing the same

1. A semiconductor storage device comprising:

a semiconductor substrate;

a plurality of memory cells formed on the semiconductor substrate, each of the plurality of memory cells including a transistor and a capacitor;

a plurality of bit lines extending in a first direction;

a plurality of word lines extending in a second direction which is different from the first direction; and

a plurality of sense amplifiers including a first sense amplifier and a second sense amplifier,

wherein the plurality of memory cells includes:

a first memory cell group sharing a first auxiliary word line; and

a second memory cell group sharing a second auxiliary word line,

wherein the plurality of word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line,

the first word line is coupled to the first auxiliary word line in a first word line contact region,

the second word line is coupled to the second auxiliary word line in a second word line contact region,

the plurality of bit lines includes a first bit line and a second bit line respectively provided on both sides of the first word line contact region, and

the first bit line and the second bit line are coupled to the first sense amplifier.

2. The semiconductor storage device according to claim 1 , wherein the first auxiliary word line includes a first gate electrode corresponding to a transistor included in at least one of the plurality of memory cells, and the second auxiliary word line includes a second gate electrode corresponding to a transistor included in at least one of the plurality of memory cells.

3. The semiconductor storage device according to claim 1 , wherein the transistor includes a first diffusion region and a second diffusion region which are formed below both sides of the gate electrode respectively,

the first diffusion region includes a bit line contact region coupled to one of the plurality of bit lines, and

the second diffusion region is coupled to the capacitor.

4. The semiconductor storage device according to claim 1 , further comprising:

a plurality of first regions which extend in the first direction and are arranged at a predetermined spacing in the second direction in the first memory cell group and the second memory cell group,

wherein a first spacing between the first regions adjacent to each other in the second direction in one of the first memory cell group and the second memory cell group is shorter than a second spacing between the first regions which are adjacent to each other in the second direction and belong to one of the first memory cell group and the second memory cell group, respectively.

5. The semiconductor storage device according to claim 3 , further comprising:

an element isolation region surrounding the first diffusion region and the second diffusion region,

wherein the capacitor is formed in a portion of the element isolation region, which includes an exposed sidewall of an active region.

6. The semiconductor storage device according to claim 3 , further comprising

a third memory cell group included in the plurality of memory cells which shares a third auxiliary word line extending in the second direction and sharing as gate electrodes of the transistors,

wherein the plurality of word lines include a third word line coupled to the third auxiliary word line,

the third word line is coupled to the third auxiliary word line in a third word line contact region,

the first memory cell group is arranged on one side of the bit line contact region and the third memory cell group is arranged on the other side of the bit line contact region,

the first word line contact region is arranged in the second direction at one end of the first auxiliary word line or the third auxiliary word line, and

the third word line contact region is arranged in the second direction at an opposite end of the first auxiliary word line or the third auxiliary word line.

7. The semiconductor storage device according to claim 1 , further comprising:

a third bit line and a fourth bit line which are included in the plurality of bit lines and are coupled to the second sense amplifier;

a second region where the third bit line and the fourth bit line are not adjacent each other; and

a third region where a third word line contact region is provided between the third bit line and the fourth bit line.

8. The semiconductor storage device according to claim 3 , further comprising

a plurality of first regions which extend in the first direction and are arranged at a predetermined spacing in the second direction within each of the first memory cell group and the second memory cell group,

wherein the capacitor includes an opposite electrode, and

an active region including the first diffusion region and the second diffusion region includes a fourth region which is bent from the first region and is arranged under the opposite electrode.

9. The semiconductor storage device according to claim 8 , wherein a bent position of the fourth region differs for each of active regions that are arrayed side by side in the second direction within the first memory cell group and includes the first diffusion region and the second diffusion region.

10. The semiconductor storage device according to claim 8 , wherein the fourth regions are arranged at a predetermined spacing under the opposite electrode.

11. The semiconductor storage device according to claim 1 , wherein four of the plurality of bit lines are coupled to the first memory cell group, and four of the plurality of bit lines are coupled to the second memory cell group.

12. The semiconductor storage device according to claim 1 , further comprising:

a first wiring layer from which the plurality of bit lines are formed;

a second wiring layer formed over the first wiring layer;

a word auxiliary wiring formed from the second wiring layer and coupled to the gate electrode; and

a third wiring layer which is formed over the second wiring layer and from which the word line coupled to the word auxiliary wiring is formed.