Systems and methods for reducing frequency pulling in an oscillator circuit
View Patent ↗Methods and systems are provided to calibrate an oscillator circuit to reduce frequency pulling as a result of a change in power to a portion of the oscillator circuit. In an embodiment, an oscillator is coupled to a clock buffer circuit and a tuning capacitor configured to tune a frequency of the oscillator to a baseline frequency required for cellular communications. A change in power to the clock buffer circuit initiates a change in an amount of capacitance seen by the oscillator, which negatively impacts the tuning of the oscillator. A register stores a frequency offset caused by the change in power, and the tuning capacitor is adjusted, using the frequency offset, in response to the change in power, such that the total amount of capacitance seen by the oscillator is not changed when the change in power occurs.
1. An oscillator circuit comprising:
an oscillator having an oscillation frequency;
a plurality of clock buffer circuits coupled to an output of the oscillator, including;
a first clock buffer circuit, wherein a first change in power to the first clock buffer circuit in the plurality of clock buffer circuits causes a first frequency offset in the oscillator frequency, and
a second clock buffer circuit, wherein a second change in power to the second clock buffer circuit causes a second frequency offset in the oscillator frequency;
a register configured to store the first frequency offset and the second frequency offset; and
a tuning capacitor coupled to the oscillator, wherein the tuning capacitor is configured to tune the oscillation frequency of the oscillator to a desired baseline frequency, wherein the tuning capacitor is adjusted, based on the respective first and second frequency offsets, in response to the respective first and second changes in power.
2. The oscillator circuit of claim 1 , wherein the oscillator is a digitally compensated crystal oscillator (DCXO) core.
3. The oscillator circuit of claim 1 , wherein the first clock buffer circuit comprises a clock buffer capacitor, wherein the first change in power to the first clock buffer circuit initiates a change in capacitance of the clock buffer capacitor, and wherein the change in capacitance of the clock buffer capacitor initiates the change in the oscillation frequency of the oscillator.
4. The oscillator circuit of claim 1 , wherein the first clock buffer circuit is changed from an off-state to an on-state to initiate the first change in power.
5. The oscillator circuit of claim 1 , wherein the first clock buffer circuit is changed from an off-state to a standby state or from a standby state to an on-state to initiate the first change in power.
6. The oscillator circuit of claim 1 , wherein the register is further configured to store a temperature value caused by the first change in power, and wherein the tuning capacitor is adjusted, using the temperature value, in response to the first change in power.
7. The oscillator circuit of claim 1 , wherein the register is further configured to store a third frequency offset caused by a third change in the oscillation frequency of the oscillator, wherein the third change in the oscillation frequency is initiated by the first change in power and the second change in power, and wherein the tuning capacitor is adjusted, using the third frequency offset, in response to the first change in power and the second change in power.
8. The oscillator circuit of claim 1 , further comprising a controller, wherein the controller is configured to:
detect a request for a first clock signal from the first clock buffer circuit; and
initiate tuning of the oscillation frequency in response to detecting the request for the first clock signal.
9. An oscillator circuit comprising:
an oscillator having an oscillation frequency;
a plurality of clock buffer circuits coupled to the oscillator including a first clock buffer circuit and a second clock buffer circuit;
a register configured to:
store a first value corresponding to a first change in capacitance, of the first clock buffer circuit in the plurality of clock buffer circuits, seen by the oscillator, wherein the first change in capacitance is initiated by a first change in power to the first clock buffer circuit, and
store a second value corresponding to a second chance in capacitance, of the second clock buffer circuit, seen by the oscillator, wherein the second change in capacitances initiated by a second change in power to the second clock buffer circuit; and
a tuning circuit coupled to the oscillator, wherein the tuning circuit is configured to tune the oscillation frequency of the oscillator to a desired baseline frequency, wherein the tuning circuit is adjusted, based on the respective first and second values, in response to the respective first and second changes in power.
10. A method comprising:
measuring a first value corresponding to a first change in capacitance seen by an oscillator, wherein the first change in capacitance is initiated by a first change in power to a first portion of a load circuit, wherein the first portion includes a first clock buffer of a plurality of clock buffers coupled to the oscillator;
storing the first value;
adjusting, using the first value, an oscillator tuning circuit in response to the first change in power;
measuring a second value corresponding to a second change in capacitance seen by the oscillator, wherein the second change in capacitance is initiated by a second change in power to a second portion of the load circuit;
storing the second value; and
adjusting, using the second value, the oscillator tuning circuit in response to the second change in power.
11. The method of claim 10 , wherein the first change in power is a change in power from an off-state to an on-state or from an on-state to an off-state.
12. The method of claim 11 , further comprising:
receiving a request for a signal from the first clock buffer; and
transmitting the signal, using the first clock buffer, wherein the first change in power is initiated by a transmission of the signal.
13. The method of claim 12 , further comprising:
changing the first clock buffer from the off-state to the on-state in response to the request for the signal; and
changing the first clock buffer from the on-state to the off-state in response to the transmission of the signal.
14. The method of claim 10 , wherein the first change in power is a change in power from an off-state to a standby state or from a standby state to an on-state.
15. The method of claim 10 , further comprising:
measuring a change in temperature caused by the first change in power;
storing a third value corresponding to the change in temperature; and
adjusting, using the third value, the oscillator tuning circuit in response to the first change in power.
16. The method of claim 10 , wherein the first value is a frequency offset caused by the first change in power.
17. The method of claim 10 , wherein the first value is a difference in capacitance seen by the oscillator caused by the first change in power, and wherein a capacitance of the oscillator tuning circuit is subtracted by the first value to adjust the oscillator tuning circuit in response to the first change in power.
18. The method of claim 10 , further comprising:
measuring a third value corresponding to a third change in capacitance seen by the oscillator, wherein the third change in capacitance is initiated by:
the first change in power to the first portion of the load circuit, and
the second change in power to the second portion of the load circuit;
storing the third value; and
adjusting, using the third value, the capacitance of the oscillator tuning circuit in response to:
the first change in power to the first portion of the load circuit, and
the second change in power to the second portion of the load circuit.
19. An oscillator circuit comprising:
an oscillator having an oscillation frequency;
a first clock buffer circuit coupled to the oscillator;
a second clock buffer circuit coupled to the oscillator;
a register configured to:
store a first value corresponding to a first change in capacitance of the first clock buffer circuit seen by the oscillator, wherein the first change in capacitance is initiated by a first change in power of the first clock buffer circuit, and
store a second value corresponding to a second change in capacitance of the second clock buffer circuit seen by the oscillator, wherein the second change in capacitance is initiated by a second change in power of the second clock buffer circuit; and
a tuning circuit coupled to the oscillator, wherein the tuning circuit is configured to tune the oscillation frequency of the oscillator to a desired baseline frequency, wherein the tuning circuit is adjusted, based on a stored value, in response to the first change in power or the second change in power.
20. The oscillator circuit of claim 19 , further comprising a controller, wherein the controller is configured to:
monitor the first clock buffer circuit, detect the first change in power, and initiate tuning the oscillation frequency based on the first value; and
monitor the second clock buffer circuit, detect the second change in power, and initiate tuning the oscillation frequency based on the second value.
21. The oscillator circuit of claim 19 , wherein the first change in power and the second change in power are changes in power from an on-state to an off-state.
22. The oscillator circuit of claim 19 , wherein the first change in power and the second change in power are changes in power from a standby state to an on-state.