Method and apparatus for changing microcode to be executed in a processor
View Patent ↗A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory addresses with associated control flags, executable instruction codes, and tag information. In the event that a comparison against the current program counter succeeds, then execution is altered as required per the control flags. If no comparison match is made, then execution of the instruction that was accessed by the program counter is executed.
1. A hot patch system comprising:
a read only memory storing a plurality of instructions;
a cache memory storing alternate instructions for at least one instruction stored within the read only memory, each cache line within the cache memory having associated therewith one or more selection flags;
a program counter coupled to the read only memory and to the cache memory, the program counter transmitting an address to both the read only memory and the cache memory; and
cache control logic coupled to the cache memory, the cache control logic comparing selected information associated with an instruction stored at the address in the read only memory with counterpart selected information associated with an instruction stored at the address in the cache memory, wherein the selected information and counterpart selected information are selected based upon the one or more selection flags associated with a cache line corresponding to the address.
2. The hot patch system according to claim 1 , wherein the one or more selection flags include a first flag indicating whether the cache control logic is to compare addresses and a second flag indicating whether the cache control logic is to compare opcodes.
3. The hot patch system according to claim 2 , wherein the second flag, when set, indicates that the cache control logic is to compare an opcode stored at the address within the read only memory with an opcode stored at the address within the cache memory.
4. The hot patch system according to claim 2 , wherein the first and second flags may be individually set, so that both flags may be set, one flag may be set while the other flag is not set, or both flags may be not set.
5. The hot patch system according to claim 2 , wherein the one or more selection flags further include a third flag indicating whether an opcode comparison should be performed for every instance of an opcode within the read only memory.
6. The hot patch system according to claim 1 , wherein each cache line within the cache memory has associated therewith one or more instruction flow control flags, wherein the cache control logic causes a change in instruction flow based upon the one or more instruction flow control flags associated with the cache line corresponding to the address when there is a comparison match between the selected information and the counterpart selected information.
7. The hot patch system according to claim 6 , wherein the one or more instruction flow control flags include an insert flag indicating that an opcode at the address within the cache memory is to be inserted prior to execution of an opcode at the address within the read only memory.
8. The hot patch system according to claim 6 , wherein the one or more instruction flow control flags include a replace flag indicating that an opcode at the address within the cache memory is to be executed instead of an opcode at the address within the read only memory.
9. The hot patch system according to claim 6 , wherein the one or more instruction flow control flags include a block flag indicating that more than one opcode starting at the address within the cache memory are to be executed instead of or before an opcode at the address within the read only memory.
10. The hot patch system according to claim 6 , wherein the one or more instruction flow control flags include a noop flag indicating that an opcode at the address within the read only memory is to be skipped.
11. A processor-implemented hot patch method, comprising:
storing a plurality of instructions within a read only memory;
storing alternate instructions for at least one instruction in the read only memory within a cache memory, each cache line within the cache memory having associated therewith one or more selection flags;
transmitting an address to both the read only memory and the cache memory; and
comparing selected information associated with an instruction stored at the address in the read only memory with counterpart selected information associated with an instruction stored at the address in the cache memory, wherein the selected information and counterpart selected information are selected based upon the one or more selection flags associated with a cache line corresponding to the address.
12. The hot patch method according to claim 11 , wherein the one or more selection flags include a first flag indicating whether addresses are to he compared and a second flag indicating whether opcodes are to be compared.
13. The hot patch method according to claim 12 , wherein the second flag, when set, indicates that an opcode stored at the address within the read only memory is to be compared with an opcode stored at the address within the cache memory.
14. The hot patch method according to claim 12 , wherein the first and second flags may be individually set, so that either both flags may be set, one flag may be set while the other flag is not set, or both flags may be not set.
15. The hot patch method according to claim 12 , wherein the one or more selection flags further include a third flag indicating whether an opcode comparison should be performed for every instance of an opcode within the read only memory.
16. The hot patch method according to claim 11 , wherein each cache line within the cache memory has associated therewith one or more instruction flow control flags, wherein instruction flow is changed based upon the one or more instruction flow control flags associated with a cache line corresponding to the address when there is a comparison match between the selected information and the counterpart selected information.
17. The hot patch method according to claim 16 , wherein the one or more instruction flow control flags include an insert flag indicating that an opcode at the address within the cache memory is to be inserted prior to execution of an opcode at the address within the read only memory.
18. The hot patch method according to claim 16 , wherein the one or more instruction flow control flags include a replace flag indicating that an opcode at the address within the cache memory is to be executed instead of an opcode at the address within the read only memory.
19. The hot patch method according to claim 16 , wherein the one or more instruction flow control flags include a block flag indicating that more than one opcode starting at the address within the cache memory are to be executed instead of or before an opcode at the address within the read only memory.
20. The hot patch method according to claim 16 , wherein the one or more instruction flow control flags include a noop flag indicating that an opcode at the address within the read only memory is to be skipped.
21. A hot patch system, comprising:
a read only memory storing a plurality of instructions;
a cache memory storing alternate instructions for at least one instruction stored within the read only memory, each cache line within the cache memory having associated therewith one or more selection flags and one or more instruction flow control flags; and
cache control logic coupled to the cache memory, the cache control logic comparing selected information associated with an instruction stored at a specified address in the read only memory with counterpart selected information associated with an instruction stored at the specified address in the cache memory,
wherein the selected information and counterpart selected information are selected based upon the one or more selection flags associated with a cache line corresponding to the specified address, and
wherein the cache control logic causes a change in instruction flow based upon the one or more instruction flow control flags associated with the cache line corresponding to the address when there is a comparison match between the selected information and the counterpart selected information.
22. The hot patch system according to claim 21 , wherein the one or more selection flags include:
a first flag indicating whether the cache control logic is to compare the specified address with an address of one or more instructions within the cache memory;
a second flag indicating whether the cache control logic is to compare an opcode stored at least at the specified address within the read only memory with an opcode stored at the specified address within the cache memory; and
a third flag indicating whether the cache control logic is to compare an opcode stored at any address within the read only memory with an opcode stored at the specified address within the cache memory.
23. The hot patch system according to claim 21 , wherein the one or more instruction flow control flags include:
a replace flag indicating that an opcode at the specified address within the cache memory is to be executed instead of an opcode at the specified address within the read only memory;
a block flag indicating that more than one opcodes starting at the specified address within the cache memory are to be executed instead of or before an opcode at the specified address within the read only memory; and
a noop flag indicating that an opcode at the specified address within the read only memory is to be skipped.
24. A processor-implemented method of executing instructions, comprising:
storing an instruction address compare value at a first instruction address in a cache memory store configured to hold alternate instructions for at least one instruction stored within a read only memory, each cache line within the cache memory store having associated therewith one or more selection flags;
receiving the first instruction address for an instruction within the read only memory from a program counter at the read only memory and the cache memory store;
based on one or more selection flags associated with a cache line at the first instruction address within the cache memory store, selecting and comparing the first instruction address with the instruction address compare value; and
selectively executing at least one instruction from a second instruction address, or executing a trap, if the first instruction address matches the instruction address compare value.
25. The method of claim 24, further comprising executing a trap if a predetermined sub-set of the bits comprising the program counter value match a corresponding sub-set of bits in the instruction address compare value.
26. A processor-implemented method of executing instructions, comprising:
storing an instruction opcode compare value at a first instruction address in a cache memory store configured to hold alternate instructions for at least one instruction stored within a read only program memory, each cache line within the cache memory store having associated therewith one or more selection flags;
receiving the first instruction address from a program counter;
retrieving a first instruction opcode from the read only program memory at the first instruction address;
based on one or more selection flags associated with a cache line at the first instruction address within the cache memory store, selecting and comparing the first instruction opcode with the instruction opcode compare value; and
executing at least one instruction from a second instruction address if the first instruction opcode matches the instruction opcode compare value.
27. A processor-implemented method of executing instructions, comprising:
storing an instruction opcode compare value at a first instruction address in a cache memory store configured to hold alternate instructions for at least one instruction stored within a read only program memory, each cache line within the cache memory store having associated therewith one or more selection flags;
receiving the first instruction address from a program counter;
retrieving an instruction opcode from the read only program memory at the first instruction address;
based on one or more selection flags associated with a cache line at the first instruction address within the cache memory store, selecting and comparing the instruction opcode with the instruction opcode compare value; and
selectively executing at least one instruction from a second instruction address, or executing a trap, if the instruction opcode matches the instruction opcode compare value.
28. An apparatus, comprising:
a processor;
a program counter;
a cache memory address store configured to store an instruction address compare value and alternate instructions for at least one instruction stored within a read only memory;
a configurable selection bit associated with each cache line within the cache memory address store;
an address comparator configurable to select and compare an address from the program counter for an instruction stored at the address in the read only memory with an instruction address compare value contained at the address in the cache memory address store based on the configurable selection bit; and
control logic operable to cause execution of an instruction from an instruction address different than the instruction address compare value contained in the memory address store if the instruction address compare value contained in the cache memory address store matches the value of the program counter if the selection bit is of a first value and operable to cause execution of a trap if the selection bit is of a second value.
29. The apparatus of claim 28, further comprising a register to store a value of the program counter.
30. The apparatus of claim 28, further comprising logic to compare only a subset of bits comprising the program counter value and the instruction address compare value to cause a trap to occur upon the match of corresponding subsets of bits.
31. An apparatus, comprising:
a processor;
a program counter;
a cache memory opcode store operable to store an instruction opcode compare value and alternate instructions for at least one instruction stored within a read only memory;
a configurable selection bit associated with each line within the cache memory opcode store;
an opcode comparator configurable to select and compare an opcode retrieved from an address specified by the program counter for an instruction stored at the address in the read only memory with the opcode compare value contained in the memory opcode store based on the configurable selection bit associated within an instruction opcode at the address; and
control logic operable to cause execution of an instruction from an instruction address different than the value contained in the program counter if the instruction opcode compare value contained in the address store matches the value of a retrieved opcode if the selection bit is of a first value and operable to cause execution of a trap if the selection bit is of a second value.